| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/apollolake: Add reset code to postcar stage | Patrick Georgi | 2018-10-23 | 1 | -0/+15 |
| * | configs: add sercon port and disable pxe serial console for apu{2,3,4,5} | Piotr Król | 2018-09-16 | 5 | -0/+48 |
| * | configs: Build test verbose BDK and FIT payload support | Patrick Rudolph | 2018-08-20 | 1 | -0/+9 |
| * | configs: Add various common non-default mainboards | Patrick Rudolph | 2018-08-17 | 5 | -0/+55 |
| * | configs: add PC Engines apu2 sample configuration | Piotr Król | 2018-05-19 | 1 | -0/+10 |
| * | configs: Add intel/harcuvar FSP 2.0 sample configuration | Mariusz Szafranski | 2017-10-04 | 1 | -0/+18 |
| * | configs: Add intel/galileo test configurations | Lee Leahy | 2017-06-20 | 7 | -0/+77 |
| * | Kconfig: Add choice of framebuffer mode | Nico Huber | 2017-06-04 | 1 | -1/+1 |
| * | configs/builder: Remove pre-defined VGA bios file | Philipp Deppenwiese | 2017-01-20 | 8 | -16/+8 |
| * | configs/builder: Add Sandy/Ivy Bridge Thinkpad configurations | Philipp Deppenwiese | 2017-01-18 | 8 | -0/+152 |
| * | configs: Add some sample default configuration files | Martin Roth | 2016-12-09 | 3 | -0/+17 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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