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* tree: Drop repeated wordsAlexander Goncharov2023-02-071-1/+1
| | | | | | | | | | | | | Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Add option to compress ramstage with LZ4Martin Roth2023-01-081-7/+28
| | | | | | | | | | | | | | | | | | When ramstage is loaded asynchronously, as on the skyrim boards, the faster decompression of LZ4 allows for faster boot times than the tighter compression of LZMA. To make this change, the name of the existing ramstage_compression option needs to be updated. BUG=b:264409477 TEST=Boot skyrim, look at boot speed Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71673 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Allow mainboards to disable stage cacheReka Norman2023-01-061-1/+8
| | | | | | | | | | | | | | | | | | | On recent Intel ChromeOS devices, although S3 is still supported, only S0ix is used on user devices, so we don't care about optimising S3 resume time. Disabing the stage cache saves boot time at the cost of increasing the S3 resume time. E.g. on nissa this reduces boot time by 6 ms and increases S3 resume time by 89 ms. BUG=b:247940538, b:192032803 TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE selected. Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* build: List all Kconfigs in CBFS `config` file, compress itJulius Werner2022-11-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The coreboot build system automatically adds a `config` file to CBFS that lists the exact Kconfig configuration that this image was built with. This is useful to reproduce a build after the fact or to check whether support for a specific feature is enabled in the image. However, the file is currently generated using the `savedefconfig` command to Kconfig, which generates the minimal .config file that is needed to produce the required config in a coreboot build. This is fine for reproduction, but bad when you want to check if a certain config was enabled, since many configs get enabled by default or pulled in through another config's `select` statement and thus don't show up in the defconfig. This patch tries to fix that second use case by instead including the full .config instead. In order to save some space, we can remove all comments (e.g. `# CONFIG_XXX is not set`) from the file, which still makes it easy to test for a specific config (if it's in the file you can extract the right value, if not you can assume it was set to `n`). We can also LZMA compress it since this file is never read by firmware itself and only intended for later re-extraction via cbfstool, which always has LZMA support included. On a sample Trogdor device the existing (uncompressed) `config` file takes up 519 bytes in CBFS, whereas the new (compressed) file after this patch will take up 1832 bytes -- still a small amount that should hopefully not break the bank for anyone. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* drivers/generic/ioapic: Drop poor implementationKyösti Mälkki2022-11-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86: Drop !CPU_INFO_V2 codeArthur Heymans2022-11-071-1/+1
| | | | | | | | | | | | Now that all platforms use parallel_mp this is the only codepath used for cpu_info() local thread storage. Change-Id: I119214e703aea8a4fe93f83b784159cf86d859d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69122 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Kconfig: Allow x86 to compress pre-ram stages if not run XIPArthur Heymans2022-10-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On the intel/glkrvp compressed: - romstage: 29659 - verstage: 31303 non compressed: - romstage: 46244 - verstage: 47012 On qemu (with some additional patch to not run XIP) compressed: - romstage: 11203 non compressed: - romstage: 13924 Even with a small romstage the size improvements are substantial, which should result in a speedup when loading the stage. On the up/squared loading romstage is sped up by 9ms. TESTED: successfully boot the up/squared & google/vilboz. Change-Id: I6906c8b6df45f2433d92d2ff1d1748cc4926c73a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* coreboot: Add support for include-what-you-useMartin Roth2022-10-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The tool "include-what-you-use" analyzes each file's headers and makes recommendations for header files to add and remove. There are additional scripts as part of the package that will make these changes directly based on the recommendations, but due to the way coreboot compiles code in/out base on Kconfig options, this isn't really safe for the project to use. It is a good starting point though. To use, set the IWYU kconfig option, then build with the command: make -k Because this doesn't actually build any files, the -k option is needed or make will stop after looking at the first file. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I084813f21a3c26cac1e4e134bf8a83eb8637ff63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Revert "Kconfig: Allow x86 to compress pre-ram stages if not run XIP"Martin L Roth2022-09-201-4/+4
| | | | | | | | | | | | This reverts commit 6317aff5b3028ad44b7885b6b63263c55b5aadb3. Reason for revert: fix broken tot master Change-Id: Ie8075cf6c80448bfc957a1e1183f0283d2011b1b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67287 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Allow x86 to compress pre-ram stages if not run XIPArthur Heymans2022-09-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On the intel/glkrvp compressed: - romstage: 29659 - verstage: 31303 non compressed: - romstage: 46244 - verstage: 47012 On qemu (with some additional patch to not run XIP) compressed: - romstage: 11203 non compressed: - romstage: 13924 Even with a small romstage the size improvements are substantial, which should result in a speedup when loading the stage. On the up/squared loading romstage is sped up by 9ms. TESTED: successfully boot the up/squared & google/vilboz. Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* Add SBOM (Software Bill of Materials) GenerationMaximilian Brune2022-08-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Firmware is typically delivered as one large binary image that gets flashed. Since this final image consists of binaries and data from a vast number of different people and companies, it's hard to determine what all the small parts included in it are. The goal of the software bill of materials (SBOM) is to take a firmware image and make it easy to find out what it consists of and where those pieces came from. Basically, this answers the question, who supplied the code that's running on my system right now? For example, buyers of a system can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore, one can quickly check to see if the firmware is subject to a new vulnerability included in one of the software parts (with the specified version) of the firmware. Further reference: https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM, intel ME and compiler (gcc,clang,other) - Add Kconfig entries to optionally supply a path to CoSWID tags instead of using the default CoSWID tags - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* src/Kconfig: src/soc/*/Kconfig files are gone, remove the includeMartin Roth2022-06-241-1/+0
| | | | | | | | | | | | | The previous two patches removed all of the soc/Kconfig files, so there is nothing to include anymore. Get rid of the 'source' command that includes them. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I95067c4702ef25a8a6db4d480c089f06986ce9b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65329 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc: Get rid of most src/soc/Kconfig filesMartin Roth2022-06-241-0/+2
| | | | | | | | | | | | | | | Most of the src/soc/Kconfig files are only there for AMD and Intel to load the main SoC Kconfig files before any common files. That can be done in src/Kconfig instead. Moving the loads to the lower level allows the removal of all but the Intel soc/Kconfig file, which can be removed in a follow-on patch. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* src/Kconfig: Fix a spelling issueMartin Roth2022-05-301-1/+1
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ibba8558dd1825a864b427097aff8552933cc6fc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Kconfig: Mark clang as ready to use on some archArthur Heymans2022-05-281-4/+16
| | | | | | | | | | | | | | | | | | This adds 2 flags: * invisible opt-in flag for platforms on which clang seems to work * visible opt-in flag to allow experimenting Clang seems to work rather well on x86_32 so it makes sense to start adding that to Jenkins buildtesting, which this allows. This allows abuild to differentiate between targets that are known to build with clang. This makes buildtesting just those targets easier. Change-Id: I46f1bad59bda94f60f4a141237ede11f6eb93cc2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* Kconfig: Increase x86 postcar & ramstage stackArthur Heymans2022-05-251-1/+1
| | | | | | | | | | | | | | | Currently the BSP stack overflows into the next AP stack. This symbols needs to be a power of 2 for alignment on the legacy smp init codepath. This fixes cpu_info on AP #1 build being broken due to stack overflow. Change-Id: Ib59d354beabc8877f09f768004ced22234ec7d72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* Kconfig: Have CONFIG_ASAN depend on COMPILER_GCCArthur Heymans2022-05-131-0/+1
| | | | | | | | | | -fsanitize=kernel-address is not implemented in clang Change-Id: Ib8660bf99b940ff9eac7461f5946df0891dd3a4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Kconfig: Add an option to skip adding a cbfs bootblock on x86Arthur Heymans2022-05-121-0/+6
| | | | | | | | | | Some targets don't need this as the bootblock is loaded differently. Change-Id: Ia42448f7e9dd0635c72857fbc1fab54508932721 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Kconfig: Make HAVE_EM100_SUPPORT invisibleArthur Heymans2022-04-191-1/+1
| | | | | | | | | | | This is a property of a platform and should not be exposed to the user. Change-Id: I34f9097d40b2bf732cecf30bf13ba5a413dd53a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/Kconfig: Update the path to 'c_start.S' for GDB_STUB configElyes Haouas2022-02-221-1/+1
| | | | | | | | Change-Id: Ib31defde0d4983a9418f05e0b812a7bbbe4fe2b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is setMarc Jones2021-11-131-1/+1
| | | | | | | | | | | | | Show the DEBUG_FUNC option if COSOLE_OVERRIDE_LOGLEVEL is set, or it will never be available for some mainboards. This was missed in commit cf3dcd6d2975673622c3272e0d7f3e421051fe74 Change-Id: Id2ef287fb39989007f28fc6475209eda0a63c792 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* src/lib: Add FW_CONFIG_SOURCE_VPDWonkyu Kim2021-11-081-0/+10
| | | | | | | | | | | | | | | | | | Read fw_config value from VPD. This new option can be used where chrome EC is not supported like pre-silicon platform and fw_config can be updated by VPD tool in OS. TEST= boot to OS and read fw_config from vpd 1. Boot to OS 2. Write "fw_config" in VPD ex) vpd -i "RW_VPD" -s "fw_config"="1" 3. reboot and check fw_config value from coreboot log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/lib/fw_config: Change fw_config sources priorityWonkyu Kim2021-11-081-10/+11
| | | | | | | | | | | | | | | | Request fw_config values from various sources (as enabled via Kconfig) until a valid value has been read. With this change, Chrome EC CBI takes precedence over CBFS fw_config. TEST=select both configs and check fallback behavior. 1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS 2. check log for reading fw_config from CBI and CBFS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUERaul E Rangel2021-11-041-4/+4
| | | | | | | | | | | | | This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* SMBIOS/SCONFIG: Allow devtree-defined Type 41 entriesAngel Pons2021-11-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the `smbios_dev_info` devicetree keyword to specify the instance ID and RefDes (Reference Designation) of onboard devices. Example syntax: device pci 1c.0 on # PCIe Port #1 device pci 00.0 on smbios_dev_info 6 end end device pci 1c.1 on # PCIe Port #2 device pci 00.0 on smbios_dev_info 42 "PCIe-PCI Time Machine" end end The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using this syntax to control the generated Type 41 entries. When this option is enabled, Type 41 entries are only autogenerated for devices with a defined instance ID. This avoids having to keep track of which instance IDs have been used for every device class. Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not enabled will result in a build-time error, as the syntax is meaningless in this case. This is done with preprocessor guards around the Type 41 members in `struct device` and the code which uses the guarded members. Although the preprocessor usage isn't particularly elegant, adjusting the devicetree syntax and/or grammar depending on a Kconfig option is probably even worse. Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki2021-10-221-0/+1
| | | | | | | | | | | | | | | For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* lib/thread: Switch to using CPU_INFO_V2Raul E Rangel2021-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1 cpu_info struct per cpu. This means that we no longer need to allocate it at the top of each threads stack. We can now in theory remove the CONFIG_STACK_SIZE alignment on the thread stack sizes. We can also in theory use threads in SMM if you are feeling venturesome. BUG=b:194391185, b:179699789 TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/kconfig: Add pre-built parserPatrick Georgi2021-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | It avoids the dependency on bison/flex, minimally speeds up the build and also works around weird race conditions in some versions of bison that need more investigation. The issue this avoids manifests as a build error when creating parser.tab.c: input in flex scanner failed make: *** [util/kconfig/Makefile.inc:66: build/util/kconfig/parser.tab.c] Error 2 Since the error happens within bison the alternative would be to make bison part of our crossgcc environment to ensure that no broken OS build is used. BUG=b:197515860 TEST=things build with bison not installed Change-Id: Ib35dfb7beafc0a09dc333e962b1e3f33df46a854 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* option: Allow mainboards to implement the APIAngel Pons2021-05-281-0/+15
| | | | | | | | | | | | | | | Some mainboards need a mainboard-specific mechanism to access option values. Allow mainboards to implement the option API. Also, add some documentation about the current option API, and describe when should one reimplement the option API in mainboard code: only when the code is mainboard-specific to comply with externally-imposed constraints. Change-Id: Idccdb9a008b1ebb89821961659f27b1c0b17d29c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* option: Turn CMOS option backend into choiceAngel Pons2021-05-281-0/+9
| | | | | | | | | | | | | In order to add more option backends, transform the current CMOS option backend into a Kconfig choice. Replace the `select` directives, as they cannot be used with choice options. Change-Id: Id3180e9991f0e763b4bae93a92d40668e7fc99bc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbolAngel Pons2021-05-181-0/+5
| | | | | | | | | | | | | | | Mainboards with variants may not always use the same cmos.layout file. Turn the hardcoded path into a Kconfig symbol to allow changing it. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus P8H61-M PRO produces an identical coreboot image. Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/drivers/ipmi: Add DEBUG_IPMI optionMarc Jones2021-04-181-0/+7
| | | | | | | | | | | IPMI debug was extra spewy, so add a debug option as SPI and other drivers have when they need to be debugged. Change-Id: I788d67c242cac23bde9750aa3e95e3276c3f1fd7 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* southbridge: Ensure common Kconfig gets included lastAngel Pons2021-02-181-0/+1
| | | | | | | | Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessorsAngel Pons2021-02-071-0/+1
| | | | | | | | | | | | | These accessors can be reused for several other northbridges. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Show console debug options if loglevel override is setMarc Jones2020-12-111-3/+3
| | | | | | | | | | | | | Show console debug options that would only be available if console SPEW was selected when the override loglevel option is selected. Change-Id: I2fb22562688d6b0bc9235c9ebe5d427dc2a67767 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
* lib/trace: Remove TRACE supportKyösti Mälkki2020-12-021-12/+1
| | | | | | | | | | | | | | | | | | | | | Looks like the option is generally not compatible with garbage collections. Nothing gets inlined, for example is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass even if we set SMP=n. Also the addresses of relocatable ramstage are currently not normalised on the logs, so util/genprof would be unable dress those. Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/xeon_sp: Move function debug macrosMarc Jones2020-10-291-0/+10
| | | | | | | | | | | | | | | Move the macros for printing debug information to debug.h in the common console include directory and device include file. These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8. The macros could be used by any platform. Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* include/device/device.h: Move resource debug macrosMarc Jones2020-10-291-0/+9
| | | | | | | | | | | | | | | Add general debug macros that print resource information. These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8. The macros are helpful in debugging complex resource allocation with multiple buses. The macros are moved from soc/intel/xeon_sp, where they were originally developed. Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie2020-10-191-0/+1
| | | | | | | | | | | | | | | | The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Rename EM100Pro-specific SPI console Kconfig optionAngel Pons2020-10-131-1/+1
| | | | | | | | | | | | To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this option with `EM100Pro`. Looks like it is not build-tested, however. Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* sconfig: Allow chipset to provide a base devicetreeDuncan Laurie2020-10-091-0/+11
| | | | | | | | | | | | | | | | | | | | | | | This change extends the devicetree override one more layer and allows the chipset to provide the base devicetree. This allows the chipset to assign alias names to devices as well as set default register values. This works for both the baseboard devicetree.cb as well as variant overridetree.cb. chipset.cb: device pci 15.0 alias i2c0 off end devicetree.cb: device ref i2c0 on end BUG=b:156957424 Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
* treewide/Kconfig: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
| | | | | | | | Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Kconfig: Update ASan config optionsHarshit Sharma2020-08-211-9/+23
| | | | | | | | | | | | | | | | | Instead of enabling ASAN_IN_ROMSTAGE from Kconfig file in a platform's dedicated directory, let's introduce a new config option HAVE_ASAN_IN_ROMSTAGE to denote if a given platform supports ASan in romstage. Similary, use HAVE_ASAN_IN_RAMSTAGE to indicate if a given platform supports ASan in ramstage. Consequently, we no longer have to make ASan x86 specific. Change-Id: I36b144305465052718f245cacf61d3ca44dfb4b4 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* lib: Add ASan support to romstage on x86 archHarshit Sharma2020-08-211-0/+7
| | | | | | | | | | | | | | This patch adds ASan support to romstage on x86 architecture. A Kconfig option is added to enable ASan in romstage. Compiler flags are updated. A memory space representing the shadow region is reserved in linker section. And a function call to asan_init() is added to initialize shadow region when romstage loads. Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* lib: Update ASan compiler flags and Kconfig help textHarshit Sharma2020-08-211-0/+5
| | | | | | | | | | | | | An additional compiler flag is added to make use of the shadow offset callback feature we introduced in our GCC patch. Also, a comment is added to tell user that this GCC patch needs to be applied in order to use ASan. Change-Id: Ia187e4991bf808f4ae137eff0ffdb9baea0085e9 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* lib: Add ASan stubHarshit Sharma2020-08-211-0/+13
| | | | | | | | | | | | Add a Kconfig option to enable address sanitizer on x86 architecture. Create ASan dummy functions. And add relevant gcc flags to compile ramstage with ASan. Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* arch/x86: Remove RELOCATABLE_RAMSTAGEKyösti Mälkki2020-07-061-13/+1
| | | | | | | | | | | | | | We always have it, no need to support opting-out. For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage located inside CBMEM, which is only true with ARCH_X86. Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Fix warningBenjamin Doron2020-07-011-1/+1
| | | | | | | | | | Add closing quotation mark to fix Kconfig warning. Change-Id: I75e8d23b81266553d7c40de7f52c6c03107c43de Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Add qc_blobs repositoryJulius Werner2020-06-301-0/+20
| | | | | | | | | | | | | | | | | | | This patch adds a separate blobs repository for Qualcomm blobs, analogous to the existing AMD blobs. Qualcomm's binary licenses allow files to be redistributed and used by anyone, but they explicitly require the user to agree to the license terms when just *downloading* the binary (even if they're not using them to build any firmware). Some community members do not like to have to agree to licenses for files they're not actually using, so we are keeping these files separate from the main blobs repository and adding an extra Kconfig to make sure the user is aware of and must explicitly agree to this before downloading these files. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD ↵Johnny Lin2020-06-281-0/+10
| | | | | | | | | | | | | | | | | | | | | variable If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source. VPD_SMBIOS_VERSION default is n. Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated from VPD. Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: insomniac <insomniac@slackware.it> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 03:56:23 +0000