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path: root/src/arch/riscv/bootblock.S
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* src/arch/riscv: Convert to SPDX license headerPatrick Georgi2020-03-061-13/+2
* riscv: Add initial support for 32bit boardsPhilipp Hug2019-02-131-1/+2
* riscv: Simplify payload handlingXiang Wang2019-02-021-0/+1
* riscv: add support to block smp in each stageXiang Wang2018-11-051-7/+3
* arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer2018-10-061-1/+1
* arch/riscv: Only execute on hart 0 for nowPhilipp Hug2018-09-141-0/+6
* riscv: add CAR interface Xiang Wang2018-07-181-15/+21
* arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer2018-02-201-1/+8
* riscv: get SBI calls to workRonald G. Minnich2017-01-161-6/+8
* riscv: Add a bandaid for the new toolchainRonald G. Minnich2016-11-021-1/+5
* RISCV: Clean up the common architectural codeRonald G. Minnich2016-10-241-4/+7
* arch/riscv: Refactor bootblock.SJonathan Neuschäfer2016-07-281-124/+19
* riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer2016-06-281-2/+2
* arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer2016-06-281-14/+1
* riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer2016-06-211-2/+5
* Change la to li (load immediate)Ronald G. Minnich2016-04-081-2/+2
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya2015-09-161-14/+94
* riscv-spike: support for Spike emulation of riscvThaminda Edirisooriya2015-08-091-15/+18
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-2/+1
* riscv: use new-style CBFS header lookupPatrick Georgi2015-04-181-19/+0
* New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner2015-04-061-1/+1
* Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich2014-12-011-0/+104
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