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* include/memlayout.h: Add OPENSBI linker macroMaximilian Brune2024-01-181-0/+5
* arch/riscv/romstage: Start from assemblyArthur Heymans2023-11-232-15/+0
* arch/risc/mcall.h: Make the stack pointer globalArthur Heymans2023-06-111-3/+3
* treewide: Remove 'extern' from functions declarationElyes Haouas2023-05-261-1/+1
* src: remove force-included header rules.h from individual filesMartin Roth2022-09-061-2/+0
* *.h: Fix up typos in guardingArthur Heymans2022-05-111-1/+1
* arch/riscv: Fix some SMP related headersKyösti Mälkki2022-01-192-3/+3
* arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relaxRaul E Rangel2021-11-251-0/+2
* arch/{arm,ppc64,riscv}: Remove cpu_infoRaul E Rangel2021-07-261-11/+0
* src/arch: Drop unneeded empty linesElyes HAOUAS2020-08-241-1/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1122-22/+0
* src/arch/riscv: Convert to SPDX license headerPatrick Georgi2020-03-0622-408/+45
* arch/*/*/early_variables.h: drop unused filesArthur Heymans2019-11-301-29/+0
* arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki2019-09-091-1/+3
* arch/non-x86: Use ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki2019-08-261-1/+1
* arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki2019-08-201-5/+1
* riscv: add support for OpenSBIXiang Wang2019-08-031-2/+7
* arch, include, soc: Use common stdint.hJacob Garber2019-07-121-79/+0
* riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengthsXiang Wang2019-06-231-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* arch/io.h: Separate MMIO and PNP opsKyösti Mälkki2019-03-041-3/+3
* riscv: Add initial support for 32bit boardsPhilipp Hug2019-02-133-7/+23
* riscv: Simplify payload handlingXiang Wang2019-02-023-3/+16
* arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer2018-12-191-0/+2
* riscv: add support for supervisor binary interface (SBI)Xiang Wang2018-11-052-0/+45
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-052-1/+50
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-111-0/+31
* Move compiler.h to commonlibNico Huber2018-10-082-3/+0
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-141-0/+10
* arch/riscv: add missing endian.h header to io.hPhilipp Hug2018-09-141-0/+1
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-142-7/+10
* riscv: update misaligned memory access exception handlingXiang Wang2018-09-101-6/+5
* riscv: update mtime initializationXiang Wang2018-09-101-0/+3
* riscv: add entry assembly file for RAMSTAGEXiang Wang2018-09-051-1/+3
* riscv: add support to check machine length at runtimeXiang Wang2018-09-051-0/+6
* riscv: add spin lock supportXiang Wang2018-09-041-0/+28
* riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang2018-09-041-3/+16
* riscv: separately define stack locations at different stagesXiang Wang2018-09-021-0/+14
* riscv: update the definition of intptr_t/uintptr_tXiang Wang2018-08-301-2/+2
* arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner2018-08-071-1/+0
* riscv: fix issues (timestrap & PRIu64)Xiang Wang2018-07-311-0/+3
* riscv: add include/arch/smp/ directoryXiang Wang2018-07-123-29/+61
* riscv: add support to check ISA extensionXiang Wang2018-07-111-0/+7
* riscv: use __riscv_atomic to check support A extensionXiang Wang2018-07-061-1/+1
* RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer2018-04-271-1/+0
* arch/riscv: Store mprv bit in size_tJonathan Neuschäfer2018-04-261-2/+2
* arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer2018-04-111-29/+0
* arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer2018-02-201-74/+224
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