coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	arch/riscv/mcall: Drop debug code	Patrick Rudolph	2019-06-28	1	-9/+0
*	riscv: Simplify payload handling	Xiang Wang	2019-02-02	1	-1/+2
*	riscv: update mtime initialization	Xiang Wang	2018-09-10	1	-3/+1
*	riscv: add include/arch/smp/ directory	Xiang Wang	2018-07-12	1	-1/+0
*	arch/riscv: Remove the current SBI implementation	Jonathan Neuschäfer	2017-12-02	1	-61/+0
*	arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers	Jonathan Neuschäfer	2017-09-27	1	-6/+3
*	riscv: Move mcall numbers to mcall.h, adjust their names	Jonathan Neuschäfer	2017-01-16	1	-12/+0
*	riscv: get SBI calls to work	Ronald G. Minnich	2017-01-16	1	-2/+23
*	arch/riscv/mcall.c: Return the correct memory base and size	Jonathan Neuschäfer	2016-12-06	1	-3/+7
*	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer	2016-11-07	1	-0/+101