| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode | Philipp Hug | 2018-10-30 | 1 | -1/+1 |
| * | arch/riscv: Advance the PC after handling misaligned load/store | Jonathan Neuschäfer | 2018-09-26 | 1 | -4/+13 |
| * | riscv: update misaligned memory access exception handling | Xiang Wang | 2018-09-10 | 1 | -0/+267 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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