| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | src/arch/riscv: Convert to SPDX license header | Patrick Georgi | 2020-03-06 | 1 | -16/+2 |
| * | riscv: add support for OpenSBI | Xiang Wang | 2019-08-03 | 1 | -0/+26 |
| * | riscv: use mret to invoke M-mode payload and disable interrupts | Xiang Wang | 2019-06-23 | 1 | -5/+20 |
| * | riscv: Use correct argument in a1 when invoking payload | Philipp Hug | 2019-02-09 | 1 | -1/+1 |
| * | riscv: Simplify payload handling | Xiang Wang | 2019-02-02 | 1 | -0/+51 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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