| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | riscv: Simplify payload handling | Xiang Wang | 2019-02-02 | 1 | -5/+6 |
| * | buildsystem: Promote rules.h to default include | Kyösti Mälkki | 2019-01-16 | 1 | -1/+0 |
| * | riscv: add support to block smp in each stage | Xiang Wang | 2018-11-05 | 1 | -0/+3 |
| * | arch/riscv: Pass the bootrom-provided FDT to the payload | Jonathan Neuschäfer | 2018-02-20 | 1 | -0/+11 |
| * | arch: remove stage_exit() | Aaron Durbin | 2016-02-11 | 1 | -16/+0 |
| * | tree: drop last paragraph of GPL copyright header | Patrick Georgi | 2015-10-31 | 1 | -4/+0 |
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 1 | -1/+1 |
| * | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich | 2014-12-01 | 1 | -0/+52 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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