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* riscv: Suppress invalid coverity errorsMartin Roth2017-02-201-0/+1
* riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer2017-01-165-46/+29
* riscv: get SBI calls to workRonald G. Minnich2017-01-165-35/+70
* riscv: enable counters via m[us]counterenRonald G. Minnich2016-12-201-10/+8
* riscv: Add support for timer interruptsRonald G. Minnich2016-12-183-4/+94
* riscv: Stub out sbi_(un)mask_interruptJonathan Neuschäfer2016-12-061-2/+4
* arch/riscv/mcall.c: Return the correct memory base and sizeJonathan Neuschäfer2016-12-061-3/+7
* riscv: map first 4GiB of physical address spaceRonald G. Minnich2016-11-201-12/+76
* riscv: add a variable to control trap managementRonald G. Minnich2016-11-141-10/+16
* riscv: change payload() to pass the config string pointer as arg0Ronald G. Minnich2016-11-131-2/+4
* riscv: start to use the configstring functionsRonald G. Minnich2016-11-123-5/+16
* riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer2016-11-074-4/+105
* riscv: Add a bandaid for the new toolchainRonald G. Minnich2016-11-023-3/+9
* RISCV: Clean up the common architectural codeRonald G. Minnich2016-10-247-31/+76
* arch/riscv: In trap handler, don't print SP twice4.5Jonathan Neuschäfer2016-10-181-2/+0
* arch/riscv: Visually align trap frame informationJonathan Neuschäfer2016-10-151-4/+4
* riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer2016-10-151-1/+0
* arch/riscv: Remove unused bootblock_simple.cJonathan Neuschäfer2016-10-151-60/+0
* riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer2016-10-151-17/+1
* riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer2016-10-151-4/+2
* RISCV: update the encoding.h file.Ronald G. Minnich2016-10-071-73/+344
* src/arch: Improve code formattingElyes HAOUAS2016-09-122-4/+4
* arch/riscv: Add missing "break;"Jonathan Neuschäfer2016-08-291-0/+1
* arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer2016-08-231-0/+47
* arch/riscv: Map the kernel space into RAM (2GiB+)Jonathan Neuschäfer2016-08-231-3/+3
* arch/riscv: Implement the SBI againJonathan Neuschäfer2016-08-235-26/+174
* arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer2016-08-231-0/+4
* arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer2016-08-231-12/+20
* arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer2016-08-231-0/+10
* arch/riscv: Print the page table structure after constructionJonathan Neuschäfer2016-08-232-9/+78
* arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer2016-08-151-62/+72
* arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer2016-08-151-1/+11
* arch/riscv: Fix the page table setup codeJonathan Neuschäfer2016-08-111-2/+5
* arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer2016-08-113-746/+829
* src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer2016-08-041-3/+3
* arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer2016-08-023-3/+42
* arch/riscv: Refactor bootblock.SJonathan Neuschäfer2016-07-283-124/+55
* arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer2016-07-281-10/+16
* arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer2016-07-281-29/+0
* arch/riscv: Enable unaligned load handlingJonathan Neuschäfer2016-07-192-3/+3
* arch/riscv: Remove enter_supervisorJonathan Neuschäfer2016-07-182-6/+0
* arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer2016-07-181-2/+4
* spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer2016-07-142-29/+0
* arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer2016-07-141-4/+2
* riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer2016-06-281-2/+2
* arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer2016-06-281-0/+2
* arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer2016-06-281-14/+1
* region: Add writeat and eraseat supportAntonello Dettori2016-06-241-1/+1
* riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer2016-06-211-2/+5
* arch/riscv: Compile with -mcmodel=medanyJonathan Neuschäfer2016-06-121-1/+4
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