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* lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARGArthur Heymans2019-11-101-1/+0
* arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans2019-11-103-6/+11
* arch/riscv: Use FDT from calling argument when using FITArthur Heymans2019-11-061-14/+4
* arch/riscv: Rename `stages.c` to `romstage.c`Nico Huber2019-11-062-10/+1
* arch/riscv: Don't link `stages.c` into ramstageNico Huber2019-11-051-1/+0
* src: Remove unused 'include <string.h>'Elyes HAOUAS2019-10-201-1/+0
* arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki2019-09-091-1/+3
* arch/non-x86: Use ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki2019-08-261-1/+1
* arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki2019-08-201-5/+1
* arch/riscv: Enable FIT supportJonathan Neuschäfer2019-08-082-0/+142
* riscv: add support for OpenSBIXiang Wang2019-08-037-11/+182
* riscv: Remove unused headersPatrick Rudolph2019-07-281-2/+0
* arch, include, soc: Use common stdint.hJacob Garber2019-07-121-79/+0
* arch/riscv: Make RISCV specific options depend on ARCH_RISCVArthur Heymans2019-07-021-11/+12
* arch/riscv/mcall: Drop debug codePatrick Rudolph2019-06-281-9/+0
* riscv: workaround selfboot putting the coreboot table into prog_entry_argXiang Wang2019-06-231-0/+7
* riscv: use mret to invoke M-mode payload and disable interruptsXiang Wang2019-06-231-5/+20
* riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengthsXiang Wang2019-06-231-1/+1
* arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_MSubrata Banik2019-06-041-2/+2
* src: Use include <console/console.h> when appropriateElyes HAOUAS2019-04-231-1/+0
* src: Add missing include 'console.h'Elyes HAOUAS2019-04-231-1/+0
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+0
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-082-3/+3
* arch/io.h: Separate MMIO and PNP opsKyösti Mälkki2019-03-041-3/+3
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-1/+1
* riscv: Add initial support for 32bit boardsPhilipp Hug2019-02-137-16/+46
* riscv: Use correct argument in a1 when invoking payloadPhilipp Hug2019-02-091-1/+1
* riscv: Show hart id in trap handlerPhilipp Hug2019-02-021-0/+2
* riscv: Simplify payload handlingXiang Wang2019-02-0210-59/+94
* riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich2019-01-241-1/+2
* riscv: create Kconfig architecture features for new partsRonald G. Minnich2019-01-172-4/+53
* buildsystem: Promote rules.h to default includeKyösti Mälkki2019-01-162-2/+0
* arch/riscv: Don't set FPU state to "dirty"Jonathan Neuschäfer2018-12-191-5/+0
* arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer2018-12-192-1/+3
* arch/riscv: Don't hardcode CSR numbers anymoreJonathan Neuschäfer2018-12-181-7/+2
* riscv: fix non-SMP supportPhilipp Hug2018-12-072-6/+6
* src: Add required space after "switch"Elyes HAOUAS2018-11-191-1/+1
* riscv: add support for supervisor binary interface (SBI)Xiang Wang2018-11-055-1/+187
* riscv: add support to block smp in each stageXiang Wang2018-11-054-8/+16
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-055-1/+144
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* riscv: simplify timer interrupt handlingPhilipp Hug2018-10-301-52/+9
* src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug2018-10-301-1/+1
* selfboot: remove bounce buffersRonald G. Minnich2018-10-111-5/+0
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-113-0/+355
* Move compiler.h to commonlibNico Huber2018-10-082-3/+0
* arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer2018-10-062-2/+2
* arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer2018-10-041-1/+6
* arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer2018-09-261-4/+13
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
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