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* arch/x86/smbios: use cpu_cpuid_extended_levelFelix Held2023-09-261-1/+1
| | | | | | | | | | | Use cpu_cpuid_extended_level instead of open-coding the same functionality in smbios_write_type4. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8e20726ea17e8ed94d5ff8f6568758fcfa162ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* arch/x86/cpu_common: use cpuid_e[a,c]xFelix Held2023-09-231-6/+2
| | | | | | | | | | | Use cpuid_eax and cpuid_ecx instead of sort-of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0dc2be4f602bf63183b9096e38403ae2f45d959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78058 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/cpu_common: use cpu_cpuid_extended_levelFelix Held2023-09-231-2/+1
| | | | | | | | | | | | Use cpu_cpuid_extended_level instead of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ea22c3997769179311f3c8822e6d8cc15a8834c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78057 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/arm64/Makefile.inc: Replace HAVE_ACPI_SUPPORT with HAVE_ACPI_TABLESMaximilian Brune2023-09-201-1/+1
| | | | | | | | | | | CONFIG_HAVE_ACPI_SUPPORT does not exist. Replace it with HAVE_ACPI_TABLES. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icc7c00dc19cae4be13e6c8cc0084a69aed8fb8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* acpi/Makefile.inc: Move code inclusionArthur Heymans2023-09-181-1/+0
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I63bbac225662377693ad5f29cc8911494c49b422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* arch/arm64: Hook up ACPI table generationArthur Heymans2023-09-182-8/+17
| | | | | | | | | | | | | Linux v6.3.5 is able to detect and use ACPI tables on an out of tree target using hacked version of u-boot to pass ACPI through UEFI. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* arch/x86: Remove libhwbase and libgfxinit .data symbols from _bssJeremy Compostella2023-09-181-13/+0
| | | | | | | | | | | | | With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section support for pre-memory stages"), the libhwbase and libgfxinit .data symbols can be moved to the .data section. Change-Id: I302391e7bc8cb4739e5801d360c57776b0e3eff6 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* x86: Add .data section support for pre-memory stagesJeremy Compostella2023-09-145-25/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86 pre-memory stages do not support the `.data` section and as a result developers are required to include runtime initialization code instead of relying on C global variable definition. To illustrate the impact of this lack of `.data` section support, here are two limitations I personally ran into: 1. The inclusion of libgfxinit in romstage for Raptor Lake has required some changes in libgfxinit to ensure data is initialized at runtime. In addition, we had to manually map some `.data` symbols in the `_bss` region. 2. CBFS cache is currently not supported in pre-memory stages and enabling it would require to add an initialization function and find a generic spot to call it. Other platforms do not have that limitation. Hence, resolving it would help to align code and reduce compilation based restriction (cf. the use of `ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot code). We identified three cases to consider: 1. eXecute-In-Place pre-memory stages - code is in SPINOR - data is also stored in SPINOR but must be linked in Cache-As-RAM and copied there at runtime 2. `bootblock` stage is a bit different as it uses Cache-As-Ram but the memory mapping and its entry code different 3. pre-memory stages loaded in and executed from Cache-As-RAM (cf. `CONFIG_NO_XIP_EARLY_STAGES`). eXecute-In-Place pre-memory stages (#1) require the creation of a new ELF segment as the code segment Virtual Memory Address and Load Memory Address are identical but the data needs to be linked in cache-As-RAM (VMA) but to be stored right after the code (LMA). Here is the output `readelf --segments` on a `romstage.debug` ELF binary. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x02000000 0x02000000 0x21960 0x21960 R E 0x20 LOAD 0x0219e0 0xfefb1640 0x02021960 0x00018 0x00018 RW 0x4 Section to Segment mapping: Segment Sections... 00 .text 01 .data Segment 0 `VirtAddr` and `PhysAddr` are at the same address while they are totally different for the Segment 1 holding the `.data` section. Since we need the data section `VirtAddr` to be in the Cache-As-Ram and its `PhysAddr` right after the `.text` section, the use of a new segment is mandatory. `bootblock` (#2) also uses this new segment to store the data right after the code and load it to Cache-As-RAM at runtime. However, the code involved is different. Not eXecute-In-Place pre-memory stages (#3) do not really need any special work other than enabling a data section as the code and data VMA / LMA translation vector is the same. TEST=#1 and #2 verified on rex and qemu 32 and 64 bits: - The `bootblock.debug`, `romstage.debug` and `verstage.debug` all have data stored at the end of the `.text` section and code to copy the data content to the Cache-As-RAM. - The CBFS stages included in the final image has not improperly relocated any of the `.data` section symbol. - Test purposes global data symbols we added in bootblock, romstage and verstage are properly accessible at runtime #3: for "Intel Apollolake DDR3 RVP1" board, we verified that the generated romstage ELF includes a .data section similarly to a regular memory enabled stage. Change-Id: I030407fcc72776e59def476daa5b86ad0495debe Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* x86/tables: Upgrade error to criticalPatrick Rudolph2023-09-121-2/+4
| | | | | | | | | | | | | When more ACPI tables are written than space is available in CBMEM, the buffer overflow corrupts other CBMEM tables and a successful boot is unlikely. Upgrade the error message to critical and be more precise what to do. Change-Id: I152842945f552905729265f7d623cd581dd0a8d0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
* soc/intel/common: Fix invalid MADT entries creationJeremy Compostella2023-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit f8ac3dda02f22ebf857efb5b845db97f00598f7d ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm walks all the `cpu_info' entries without discarding empty ones. Since `cpu_info' is not initialized, the data that is used is undefined and it generally results in the creation of invalid `Local x2APIC' entries in the MADT ("APIC") ACPI table. Depending on the X2APIC ID value the Linux kernel behavior changes (cf. arch/x86/kernel/acpi/boot.c::acpi_register_lapic()): 1. If (int)ID >= MAX_LOCAL_APIC (32768), the Linux kernel discards the entry with the "skipped apicid that is too big" INFO level message. 2. If (int)ID < MAX_LOCAL_APIC (32768) (including negative) this data is taken into account and it can lead to undesirable behavior such as core being disabled as (cf. "native_cpu_up: bad cpu" ERROR kernel message). TEST=Verified the MADT does not contain any invalid entries on rex. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77615 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella2023-09-122-2/+16
| | | | | | | | | | | | | | | | | | On Intel SoCs, if TME is supported, TME key ID bits are reserved and should be subtracted from the maximum physical addresses available. BUG=288978352 TEST=Verified that DMAR ACPI table `Host Address Width` field on rex went from 45 to 41. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella2023-09-121-0/+3
| | | | | | | | | | | | | | | | | It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/arm64: Remove space between function name and '('Elyes Haouas2023-09-112-3/+3
| | | | | | | | Change-Id: I0cba99070f251d86679c068bb737c05178f4a7c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77771 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth2023-09-082-2/+2
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/cpu: Remove unnecessary parenthesesElyes Haouas2023-08-281-4/+4
| | | | | | | | | Change-Id: I157a3a700ed998b1012c85857c5fad78f60d62dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77525 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* acpi/acpi.c: Move setting FADT SCI INT to arch specific codeArthur Heymans2023-08-021-0/+18
| | | | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic1533cb520a057b29fc8f926db38338cd3401b18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76295 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* arch/arm64: Hook up FADTArthur Heymans2023-08-022-0/+8
| | | | | | | | | | | | Arm needs very little of FADT. Just a HW reduced model bit and low power idle bit set. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76180 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpi.c: Split of ACPI table generation into separate filesArthur Heymans2023-07-211-0/+1
| | | | | | | | | | | | | | | acpi.c contains architectural specific things like IOAPIC, legacy IRQ, DMAR, HPET, ... all which require the presence of architectural headers. Instead of littering the code with #if ENV_X86 move the functions to different compilation units. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* vboot: Fix S3 resume with stage_cacheKyösti Mälkki2023-07-101-2/+2
| | | | | | | | | | | | | | | | | | | | In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not get called when postcar was loaded from TSEG stage cache on ACPI S3 resume path. Resume failed as MP init attempts to access microcode update from unverified FW_MAIN_A/B section. In a similar fashion, for POSTCAR=n, loading ramstage from TSEG stage cache would bypass the call to vboot_run_logic(). TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able to complete S3 resume. Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
* arch/x86: Ensure LAPIC mode for exception handlerKyösti Mälkki2023-07-051-3/+2
| | | | | | | | | | | Attempting to use X2APIC MSRs before the call to enable_lapic() is made raises exception and double-faults. Change-Id: Ib97889466af0fbe639bec2be730784acc015b525 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* arch/arm64/Makefile.inc: Fix Kconfig name in commentYu-Ping Wu2023-07-041-1/+1
| | | | | | | | | | Change-Id: I93860a20a425c833b41e16347722e9a879f83ab1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* arch/x86/Kconfig: remove period from DUMP_SMBIOS_TYPE17 titleEric Lai2023-06-271-1/+1
| | | | | | | | | | Option name strings should not end with a period, remove it. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Id61d8961cad2cd311db7d9da3bdb86f0f28b57b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious2023-06-234-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* arch/x86,lib: Migrate SMBIOS implementation to common codeBenjamin Doron2023-06-223-1451/+5
| | | | | | | | | | | | | | SMBIOS is not specific to architecture, and this is mostly a generic implementation. Therefore, move it to common code, having architecture-specific code define some functions to fill this data. Change-Id: I030c853f83f8427da4a4c661b82a6487938b24e6 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75886 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* arch/x86: Introduce DUMP_SMBIOS_TYPE17 configEric Lai2023-06-202-0/+66
| | | | | | | | | | | | | | | | | | DDR5 spd is not supported read by coreboot. But FSP can read it, so print the memory information from smbios type17 dimm information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/riscv: Add clang as supported architectureArthur Heymans2023-06-111-0/+1
| | | | | | | | | | | | | All emulated targets properly compile and boot to the same extent as with gcc. Change-Id: I11ddd9347c2638fb7c26cd4939aa96ff8ddd1e66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74571 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Daniel Maslowski <info@orangecms.org>
* arch/riscv: Always build opensbi with GCCArthur Heymans2023-06-111-1/+3
| | | | | | | | | | | | | Building with clang is currently broken as /usr/bin/ld.bfd is used rather than the proper crosstoolchain linker. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idd8006a26b2c2f9f777fdffe231c3c774320d805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75397 Reviewed-by: Daniel Maslowski <info@orangecms.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/risc/mcall.h: Make the stack pointer globalArthur Heymans2023-06-111-3/+3
| | | | | | | | | | | | | | Clang complains about the stack pointer register variable being uninitialized. This can remediated by making the variable global. Change the variable name to be more unambiguous. Change-Id: I24602372833aa9d413bf396853b223263fd873ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74570 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Daniel Maslowski <info@orangecms.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/include/arch/vga: add defines for VGA MMIO addressesFelix Held2023-06-061-0/+11
| | | | | | | | | | | To avoid magic constants in the code, add defines for the VGA MMIO address range from 0xa0000-0xbffff. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Reviewed-on: https://review.coreboot.org/c/coreboot/+/75618 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig optionFelix Held2023-05-271-6/+0
| | | | | | | | | | | | | Only the Intel Quark SoC selected this option and that SoC was dropped in commit 531023285ea4 ("soc/intel/quark: Drop support"), so drop this Kconfig option too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Remove 'extern' from functions declarationElyes Haouas2023-05-262-2/+2
| | | | | | | | | | | "extern" is automatically implied with function declaration. Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* arch/x86/include/arch/pci_io_cfg: add IO port count & last port definesFelix Held2023-05-251-2/+4
| | | | | | | | | | The PCI config space access via IO ports uses two 32 bit IO ports. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie99b4f5fc01fb0405243ff108d813ee1a3d35e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75408 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Don't allow hw floating point operationsArthur Heymans2023-05-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Even though coreboot does not allow floating point operations some compilers like clang generate code using hw floating point registers, e.g. SSE %XMMx registers on 64bit code by default. Floating point operations need to be enabled in hardware for this to work (CR4). Also in SMM we explicitly need to save and restore floating point registers for this reason. If we instruct the compiler to not generate code with FPU ops, this simplifies our code as we can skip that step. With clang this reduces the binary size a bit. For instance ramstage for qemu/Q35 drops from 216600 bytes decompressed to 212768. TEST: See that with x86_64 bit and clang coreboot reaches the payload without setting the CR4_OSFXSR bit in CR4. Without this change it would bootloop very early in the bootblock on Qemu Q35. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib8590c55e7aed1ece2aa23b8ea99463396435e11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75316 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* x86: pci_io_cfg: Make constant unsigned to fix out of bounds shiftPaul Menzel2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the error below when running a coreboot image built with `CONFIG_UBSAN=y`. PCI: pci_scan_bus for bus 00 shift out of bounds src/arch/x86/include/arch/pci_io_cfg.h:13:20 ubsan: unrecoverable error. GCC with `-fsanitize=shift` also flags this: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' So, make the constant unsigned. TEST=emulation/qemu-i440fx with `CONFIG_UBSAN=y` stops later with [ERROR] unaligned access src/lib/rmodule.c:152:27 [EMERG] ubsan: unrecoverable error. Change-Id: Ib05d225ab9f22078d765009b4ee6ef0c63231eed Found-by: UBSAN Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/ioapic.c: Increase the number of bits for ioapic IDArthur Heymans2023-05-141-1/+6
| | | | | | | | | | | In practice hardware can use larger numbers. Change-Id: I6e9ddd1ebd396c37e25eb3019f981d45d9c5e062 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* arch/x86/car.ld: Fix undefined macroArthur Heymans2023-05-091-1/+1
| | | | | | | | | | | | Processing LD flags is done without most warnings enabled, which is why this never caused problems. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9d82c1426a1c1d2f21c8e7560685cf9d7106a88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75033 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}Kyösti Mälkki2023-05-051-4/+5
| | | | | | | | | | | | Only expand these strings in lib/identity.o. Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki2023-04-291-0/+11
| | | | | | | | | | | | | | | | For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is setJulius Werner2023-04-272-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | walkcbfs_asm is a simple CBFS implementation in assembly to find a file on a system with memory-mapped SPI flash. It seems to be mostly unused nowadays and is only still called for early microcode loading on some old systems (e.g. FSP 1.1 and older). Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe because it does not verify the hashes the way the normal CBFS code does. Therefore, to avoid potential security vulnerabilities from creeping in, this patch makes sure the code cannot be compiled in when CBFS_VERIFICATION is active. That means it won't be supported on the old boards using this for microcode loading. Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this dependency more obvious in menuconfig, but the configs actually using this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM is just set everywhere by default although only very few boards are really using it, and a lot of different old Intel CPU models are linking in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under a single Kconfig so that's not easy to change). To keep things simple, this patch will just prevent the code from being built and result in a linker error if a bad combination of Kconfigs is used together. Later patches can clean up the Kconfigs to better wrap that dependency if the affected boards are still of enough interest to be worth that effort. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] defineFelix Held2023-04-271-12/+15
| | | | | | | | | | | | | | | | | Instead of having multiple instances of the same magic numbers in the code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA definitions. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* ACPI: Make FADT entries for SMI architecturalKyösti Mälkki2023-04-271-0/+7
| | | | | | | | | Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki2023-04-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* arch/riscv/trap_handler.c: Use new names for CSRArthur Heymans2023-04-212-2/+2
| | | | | | | | | | sbadaddr and mbadaddr are deprecated names. This fixes compilation with clang. Change-Id: I5c8fa82b6131dec10f55e8ebcf36b34e30b57bad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* arch/riscv: Fix compiler argument for clangArthur Heymans2023-04-211-2/+8
| | | | | | | | | | The suffixes zicsr and zifencei are assumed by default for clang. Change-Id: I75947f614c3600d5d9d461970159f0787fd6c3de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/amd: Clarify ACPI _PRT entry generationKyösti Mälkki2023-04-141-1/+0
| | | | | | | | | | | | The reference to a constant FCH IOAPIC interrupt count used with GNB IOAPIC was a bit obscure. Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans2023-04-061-18/+0
| | | | | | | | | | | | It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/smbios: Check str for NULL in smbios_add_string()Maximilian Brune2023-04-041-1/+1
| | | | | | | | | Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73980 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power*Krystian Hebel2023-04-032-15/+0
| | | | | | | | | | CBFS location in memory is different than on the real hardware. Change-Id: Icd806a57f449042c883b624056c05c1ff7e4c17e Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
* arch/x86/smbios: Add socket type for Meteor LakeJay Patel2023-03-291-0/+2
| | | | | | | | | | | | | | | Add socket type for Meteor Lake as PROCESSOR_UPGRADE_OTHER. BUG=None TEST=processor upgrade is equal to "Other" for "dmidecode -t 4" Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: If891990436a0679697e292b460eaec63c09e7bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* x86/include/registers.h: macros should not use a trailing semicolonYuchen He2023-03-221-4/+4
| | | | | | | | | | | | Macros should not use a trailing semicolons. Remove those from 'LONG_DOWNTO8' aswell as 'LONG_DOWNTO16' and add them at places where the macros are used. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I5ba01bc09f9a2d9ecd54014e27ec0a24c7297412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 00:22:00 +0000