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* treewide: Remove unused CHIPsArthur Heymans2024-02-203-12/+0
* arch to cpu: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1827-0/+53
* cpu/x86/64bit: Turn jumping to long mode into a macroArthur Heymans2024-02-083-5/+6
* device/device.h: Rename busses for clarityArthur Heymans2024-01-313-3/+3
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-315-5/+5
* cpu: Rename Makefiles from .inc to .mkMartin Roth2024-01-2431-1/+1
* northbridge/intel/sandybridge: Enable x86_64 for mrc.binPatrick Rudolph2024-01-051-1/+1
* Revert "cpu/intel/common: Define build time physical address reserved bits"Jeremy Compostella2023-12-222-11/+0
* cpu/intel/model_206ax: Use macro IS_IVY_CPUPatrick Rudolph2023-12-041-1/+1
* nb/intel/sandybridge: Use SA devid to identify PC typePatrick Rudolph2023-11-204-21/+0
* cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIGPatrick Rudolph2023-11-202-0/+4
* cpu/intel/model_206ax: Write MSRs in scope package only oncePatrick Rudolph2023-11-201-50/+72
* cpu/intel/model_2065x: Read CPU voltage for SMBIOSPatrick Rudolph2023-11-141-0/+1
* cpu/intel/common: Define build time physical address reserved bitsJeremy Compostella2023-10-202-0/+11
* x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella2023-10-207-0/+21
* cpu/intel/model_206ax: Only use supported C-statesPatrick Rudolph2023-10-061-5/+59
* cpu/intel/model_206ax: Use haswell cstate_mapPatrick Rudolph2023-10-062-50/+37
* cpu/intel/model_206ax: Print supported C-statesPatrick Rudolph2023-10-061-1/+21
* cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kBArthur Heymans2023-10-051-1/+1
* arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORTFelix Held2023-09-291-0/+1
* */include/cpu: use unsigned int for number of address bitsFelix Held2023-09-291-2/+2
* x86: Add .data section support for pre-memory stagesJeremy Compostella2023-09-144-0/+12
* arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella2023-09-122-0/+27
* cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella2023-09-123-0/+20
* cpu: Add SPDX license headers to MakefilesMartin Roth2023-08-0627-0/+54
* src/*/post_code.h: Change post code prefix to POSTCODEYuchen He2023-08-056-45/+45
* cpu: Get rid of CPU_SPECIFIC_OPTIONSElyes Haouas2023-08-0411-54/+21
* cpu/intel/microcode: Drop unnecessary alignment for split microcodeSubrata Banik2023-07-121-1/+1
* cpu: Enable per-CPUID microcode loading in CBFSSubrata Banik2023-07-084-5/+109
* cpu/intel/microcode: Avoid Pre-RAM microcode update if FIT enableSubrata Banik2023-07-081-0/+1
* commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious2023-06-234-8/+8
* cpu/intel/haswell: Add Broadwell Trad µcode updatesAngel Pons2023-05-271-0/+2
* cpu/Kconfig: Remove MMX config optionArthur Heymans2023-05-259-9/+0
* treewide: Add missing include guards to chip.hJan Samek2023-04-283-0/+15
* cpu/intel/speedstep: Separate single SSDT CPU entryKyösti Mälkki2023-04-261-35/+43
* cpu,soc/intel: Separate single SSDT CPU entryKyösti Mälkki2023-04-173-51/+60
* cpu,soc/intel: Sync ACPI CPU object implementationsKyösti Mälkki2023-04-143-31/+19
* cpu,soc/intel: Use acpigen_write_processor_device()Elyes Haouas2023-04-143-12/+12
* cpu/intel/speedstep: Refactor P-state coordinationKyösti Mälkki2023-04-141-7/+12
* intel/i82371eb,speedstep: Use dev_count_cpu()Kyösti Mälkki2023-04-141-13/+1
* arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held2023-02-0915-17/+15
* cpu/intel/model_206ax/model_206ax_init: use CPUID_ALL_STEPPINGS_MASKFelix Held2023-02-081-10/+2
* arch/x86/cpu: introduce and use device_match_maskFelix Held2023-02-0815-103/+114
* mb/samsung: Enable VBOOT_VBNV_FLASHYu-Ping Wu2023-02-082-2/+0
* Add option to use Ada code in romstageJeremy Compostella2022-12-171-0/+13
* cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans2022-12-163-15/+18
* cpu/intel/206ax: Fix generating C state entriesArthur Heymans2022-12-141-1/+1
* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-052-22/+3
* cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans2022-12-013-25/+6
* cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans2022-12-011-3/+14
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