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path: root/src/cpu/intel/haswell/romstage.c
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* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-12/+2
* AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth2019-09-101-2/+0
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-5/+1
* intel/haswell: Move platform_enter_postcar()Kyösti Mälkki2019-08-111-37/+0
* arch/x86: Adjust size of postcar stackKyösti Mälkki2019-07-041-3/+1
* cpu: Add missing #include <commonlib/helpers.h>Elyes HAOUAS2019-06-211-0/+1
* Move calls to quick_ram_check() before CBMEM initKyösti Mälkki2019-03-271-4/+0
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+0
* src: Drop unused '#include <halt.h>'Elyes HAOUAS2019-03-161-1/+0
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-3/+3
* src: Drop unused include <arch/acpi.h>Elyes HAOUAS2019-03-061-1/+0
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* postcar: Make more use of postcar_frame_add_romcache()Nico Huber2019-02-121-2/+1
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-091-3/+0
* nb/intel/haswell: Add support for PEGTristan Corrick2019-01-031-0/+2
* src: Remove unneeded include <cbfs.h>Elyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* intel: Use CF9 reset (part 1)Patrick Rudolph2018-10-221-8/+2
* src/*: normalize Google copyright headersPatrick Georgi2018-09-281-1/+1
* src: Get rid of non-local header treated as localElyes HAOUAS2018-08-131-5/+5
* drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese2018-07-251-3/+0
* cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans2018-06-141-29/+2
* cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans2018-06-051-92/+25
* security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese2018-06-041-3/+3
* security/tpm: Change TPM naming for different layers.Philipp Deppenwiese2018-01-181-1/+1
* security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese2018-01-181-1/+1
* chromeec: Remove checks for EC in RODaisuke Nojiri2017-10-041-5/+0
* cpu/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-281-4/+4
* haswell: add CBMEM_MEMINFO table when initing RAMMatt DeVillier2017-06-161-0/+2
* cpu/intel: Fix brace issues detected by checkpatch.plLee Leahy2017-03-161-2/+1
* cpu/intel: Fix the spacing issuesLee Leahy2017-03-161-2/+2
* cpu/intel: Indent with tabsLee Leahy2017-03-161-2/+2
* CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki2016-12-061-0/+1
* romstage_handoff: remove code duplicationAaron Durbin2016-12-011-6/+1
* intel post-car: Increase stacktop alignmentKyösti Mälkki2016-11-181-3/+1
* lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin2016-10-311-10/+0
* src/cpu: Capitalize ROM and RAMElyes HAOUAS2016-07-311-3/+3
* intel/haswell post-car: Minor fix on MTRR settingKyösti Mälkki2016-07-231-2/+2
* intel/haswell: Add asmlinkage for romstage_after_car()Kyösti Mälkki2016-07-231-1/+1
* intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki2016-07-101-15/+1
* intel/haswell: No need for ACPI S3 resume backupKyösti Mälkki2016-06-291-7/+0
* intel romstage: Use run_ramstage()Kyösti Mälkki2016-06-291-2/+2
* ACPI S3: Add common recovery codeKyösti Mälkki2016-06-221-17/+2
* Ignore RAMTOP for MTRRsKyösti Mälkki2016-06-221-2/+2
* Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki2016-06-171-0/+1
* Fix some cbmem.h includesKyösti Mälkki2016-06-171-1/+1
* tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli2016-02-261-1/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc2015-10-151-4/+4
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