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* cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboardKeith Hui2020-01-181-1/+0
* AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth2019-09-102-5/+0
* Use 3rdparty/intel-microcodeArthur Heymans2019-07-011-1/+1
* src/cpu: Remove unneeded includesElyes HAOUAS2018-06-011-3/+0
* Constify struct cpu_device_id instancesJonathan Neuschäfer2017-11-231-1/+1
* src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS2016-08-231-1/+1
* src/cpu: Capitalize CPUElyes HAOUAS2016-07-311-1/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-312-8/+0
* cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc2015-09-302-4/+1
* Remove address from GPLv2 headersPatrick Georgi2015-05-212-2/+2
* 3rdparty: move to 3rdparty/blobsPatrick Georgi2015-05-051-1/+1
* 3rdparty: Move to blobsPatrick Georgi2015-05-051-1/+1
* cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc2015-02-285-815/+0
* cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc2015-02-281-6/+1
* vboot2: add verstageStefan Reinauer2015-01-271-0/+1
* {arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan2014-10-271-1/+1
* Introduce stage-specific architecture for corebootFurquan Shaikh2014-05-061-1/+3
* Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh2014-05-031-0/+1
* cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc2014-01-161-5/+0
* cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc2014-01-164-15/+16
* cpu/intel/model_67x: Add missing includeKyösti Mälkki2013-07-301-0/+1
* GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel2013-03-011-1/+1
* Get rid of drivers classPatrick Georgi2012-11-271-1/+1
* MTRR: get physical address size from CPUIDSven Schnelle2012-01-101-1/+1
* cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui2011-08-041-0/+4
* Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.Keith Hui2010-10-138-0/+922
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