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* cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-252-2/+10
* Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans2019-11-251-0/+1
* intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMERKyösti Mälkki2019-11-051-1/+2
* cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki2019-11-031-0/+1
* AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth2019-09-104-9/+0
* arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki2019-07-091-0/+1
* cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki2019-07-091-0/+1
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki2018-06-171-0/+1
* cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki2018-06-172-3/+3
* src/cpu: Remove unneeded includesElyes HAOUAS2018-06-011-2/+0
* cpu/intel/slot_1: Increase CAR size to 8KiBKeith Hui2017-09-121-2/+2
* cpu/intel: Wrap lines at 80 columnsLee Leahy2017-03-161-19/+34
* cpu/intel: Fix brace issues detected by checkpatch.plLee Leahy2017-03-161-4/+2
* cpu/intel: Fix the spacing issuesLee Leahy2017-03-161-14/+14
* cpu/intel: Indent with tabsLee Leahy2017-03-161-1/+1
* intel post-car: Split legacy socketsKyösti Mälkki2016-11-081-1/+1
* Remove non-ascii & unprintable charactersMartin Roth2016-08-011-1/+1
* intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-211-0/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-314-16/+0
* x86: remove cpu_incs as romstage Make variableAaron Durbin2015-09-041-1/+1
* Remove address from GPLv2 headersPatrick Georgi2015-05-214-4/+4
* intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki2014-12-301-0/+4
* cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-171-1/+0
* cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-081-1/+0
* Drop redundant select CACHE_AS_RAMKyösti Mälkki2014-07-051-1/+0
* cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc2014-01-161-1/+11
* cpu: Fix spellingMartin Roth2013-07-111-3/+3
* GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel2013-03-014-4/+4
* Remove chip.h files without config structureKyösti Mälkki2012-10-072-23/+0
* Auto-declare chip_operationsKyösti Mälkki2012-08-221-2/+0
* cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui2011-08-042-0/+812
* Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.Keith Hui2010-10-161-0/+1
* Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.Uwe Hermann2010-10-151-5/+0
* Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.Keith Hui2010-10-131-0/+1
* Add missing include of model_6bx for slot_1.Keith Hui2010-10-121-0/+1
* Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann2010-10-062-0/+3
* Rename build system variables to be more intuitive, andPatrick Georgi2010-09-301-1/+1
* license header fixes Nils Jacobs2010-05-141-2/+1
* Add proper Slot 1 CPU support code/infrastructure.Keith Hui2010-03-054-0/+112
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