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* cpu/intel/socket_LGA775: Drop 'select SSE'Elyes HAOUAS2022-01-271-1/+0
* cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held2021-10-261-1/+0
* cpu/intel/socket_LGA775: Drop commented-out entriesFelix Held2021-10-262-4/+0
* cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPERFelix Held2021-10-261-1/+0
* cpu/x86: Introduce `CPU_X86_CACHE_HELPER`Felix Held2021-10-262-1/+1
* cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held2021-10-251-1/+0
* cpu/x86/tsc: Deduplicate Makefile logicAngel Pons2021-09-081-1/+0
* cpu/intel/hyperthreading: Build only for selected modelsKyösti Mälkki2021-06-071-1/+0
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-181-1/+0
* treewide [Kconfig]: Remove useless commentElyes HAOUAS2021-02-021-1/+1
* cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZEArthur Heymans2021-01-281-1/+1
* cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZEElyes HAOUAS2021-01-211-1/+1
* Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans2019-11-251-4/+0
* nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-152-0/+11
* nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans2018-06-051-4/+1
* cpu/intel/car: Prepare for some POSTCAR_STAGE supportKyösti Mälkki2018-06-021-1/+5
* cpu/intel/lga775: Do not select model_6ex CPUArthur Heymans2016-12-102-2/+0
* intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-211-0/+1
* intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-211-0/+1
* intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki2016-06-181-1/+1
* cpu: get rid of socket source codeStefan Reinauer2015-05-042-6/+0
* Fix socket LGA775Kyösti Mälkki2013-03-072-1/+1
* Add support for socket LGA775Stefan Tauner2012-10-303-0/+50
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