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* cpu/x86/mtrr/xip_cache.c: Fix inconsistent messageAngel Pons2019-11-031-1/+1
* cpu/x86: Add a prog_run hook to set up caching of XIP stagesArthur Heymans2019-11-022-0/+113
* cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ useKyösti Mälkki2019-09-281-3/+0
* AUTHORS: Move src/cpu copyrights into AUTHORS fileMartin Roth2019-09-102-8/+3
* cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()Subrata Banik2019-08-081-1/+2
* src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS2019-06-221-1/+0
* cpu: Add missing #include <commonlib/helpers.h>Elyes HAOUAS2019-06-211-0/+1
* cpu/x86/mtrr: Assert that MSR arrays are fully initializedJacob Garber2019-05-291-1/+3
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-082-4/+4
* src: Drop unused include <arch/acpi.h>Elyes HAOUAS2019-03-061-1/+0
* cpu/x86/mtrr/mtrr.c:Avoid static scan false positiveRichard Spiegel2019-02-281-0/+2
* soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber2018-11-233-7/+213
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* Correct "MTTR" to "MTRR"Jonathan Neuschäfer2018-04-111-1/+1
* cpu/x86/mtrr: Fix broken output ("indexis")Jonathan Neuschäfer2018-04-111-2/+1
* cpu/x86/mtrr: Use single code path with/without holesNico Huber2018-04-091-129/+55
* cpu/x86/mtrr: Optimize hole carving strategyNico Huber2018-04-091-34/+98
* x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRsMarshall Dawson2018-02-161-1/+29
* cpu/x86/mtrr: Remove var-MTRR alignment optimizationNico Huber2017-10-161-38/+10
* src/cpu: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-07-131-1/+1
* cpu/x86/mtrr: fail early if solution exceeds available MTRRsAaron Durbin2017-06-131-3/+15
* cpu/x86: Wrap lines at 80 columnsLee Leahy2017-03-161-3/+4
* cpu/x86: Add int to unsignedLee Leahy2017-03-161-1/+2
* cpu/x86: Use tabs for indentLee Leahy2017-03-161-14/+14
* src/cpu/x86: Update/Add license headers to all filesMartin Roth2017-02-221-0/+13
* cpu/x86/mtrr: allow temporary MTRR range during corebootAaron Durbin2016-11-121-11/+79
* cpu/x86: Move fls() and fms() to mtrr.hRizwan Qureshi2016-09-121-24/+0
* cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundaryAaron Durbin2016-07-221-8/+8
* soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov2016-04-281-0/+1
* mtrr: Define a function for obtaining free var mtrrFurquan Shaikh2016-03-181-0/+24
* cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov2016-03-161-0/+1
* cpu/x86/mtrr: remove early_mtrr_* functionsAaron Durbin2016-03-161-77/+0
* cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin2016-03-161-8/+0
* cpu/x86/mtrr: add helper function to detect variable MTRRsAaron Durbin2016-03-081-3/+10
* src: Fix various spelling and whitespace issues.Martin Roth2016-02-021-2/+2
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* cpu/x86/mtrr: Add MTRR index and total MTRRs to error messagePaul Menzel2015-10-151-1/+3
* cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc2015-10-152-26/+26
* Verify Kconfigs symbols are not zero for hex and int type symbolsMartin Roth2015-07-121-1/+1
* Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()Martin Roth2015-07-121-1/+1
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* x86/mtrr: Enable MTRR's before enabling cachingIsaac Christensen2014-09-251-4/+4
* x86: Minimize work done with the caches disabled in mtrr functions.Gabe Black2014-09-241-38/+78
* x86 MTRR: Drop unused return valueKyösti Mälkki2014-06-301-2/+1
* Use MTRR definesKyösti Mälkki2014-06-301-4/+3
* Remove CACHE_ROM.Vladimir Serbinenko2014-02-251-76/+0
* mtrr: only add prefetchable resources as WRCOMB for VGA devicesAaron Durbin2014-02-091-2/+17
* MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko2014-02-061-3/+2
* mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocationAaron Durbin2014-02-061-2/+25
* src/cpu: Fix spelling of MTTR to MTRRPaul Menzel2014-01-262-4/+4
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