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* Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki2012-03-251-4/+25
* Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki2012-03-251-13/+9
* Intel cpus: Include CAR from socketKyösti Mälkki2012-03-173-1/+2
* Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki2012-03-162-4/+7
* Fix AMD Agesa leaking KconfigKyösti Mälkki2012-03-162-8/+5
* ROMCC boards have no XIP limitPatrick Georgi2012-03-161-0/+1
* Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi2012-03-161-0/+1
* Fix address of IDT in real-mode entryKyösti Mälkki2012-03-161-7/+8
* move console includes to central console/console.hStefan Reinauer2012-03-091-10/+0
* Move C labels to start-of-linePatrick Georgi2012-03-071-1/+1
* Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.Marc Jones2012-02-201-2/+3
* Remove whitespace.Patrick Georgi2012-02-175-13/+13
* AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh2012-02-167-2/+330
* Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki2012-02-163-10/+19
* Intel model_106cx: Use symbolic names for MTRR bitsKyösti Mälkki2012-02-151-6/+6
* AMD Geode cpus: apply un-written naming rulesKyösti Mälkki2012-02-1322-33/+33
* Intel cpus: apply un-written naming rulesKyösti Mälkki2012-02-1013-21/+19
* Add Intel Socket LGA771Sven Schnelle2012-02-096-0/+31
* VIA cpus: apply un-written naming rulesKyösti Mälkki2012-02-099-17/+22
* post code: Replaced hard-coded post code with macroVikram Narayanan2012-01-231-2/+1
* trivial: spelling fixes in commentsVikram Narayanan2012-01-211-2/+2
* Leave SSE and MMX instructions enabled in corebootStefan Reinauer2012-01-202-68/+0
* MTRR: get physical address size from CPUIDSven Schnelle2012-01-1020-21/+25
* Fix Geode GX2 + LX caching for tiny bootblock.Nils Jacobs2012-01-091-2/+2
* ACPI: mark empty get_cst_entries() weakSven Schnelle2012-01-091-1/+1
* Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.Marc Jones2011-12-261-2/+1
* Use MMCONF for all AMD family 10 CPUs.Marc Jones2011-12-131-2/+5
* Bootblock does not need a unique boot_cpu()Kyösti Mälkki2011-12-051-0/+5
* Remove unused code files and cosmetic changesKyösti Mälkki2011-11-241-28/+29
* k8 raminit: add workaround for erratum #181 on non-fam-fFlorian Zumbiehl2011-11-221-1/+10
* Fix post_code in 16bit entryKyösti Mälkki2011-11-221-0/+2
* remove trailing whitespaceStefan Reinauer2011-11-0114-41/+41
* Remove XIP_ROM_BASEPatrick Georgi2011-11-0115-54/+11
* Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek2011-10-306-8/+8
* Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi2011-10-281-1/+0
* Get rid of AUTO_XIP_ROM_BASEPatrick Georgi2011-10-287-55/+37
* SPEEDSTEP: write _CST tablesSven Schnelle2011-10-251-0/+10
* Activate older Xeon P4 microcodesKyösti Mälkki2011-10-181-1/+2
* Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson2011-10-172-22/+73
* SMM: Move wbinvd after pmode jumpStefan Reinauer2011-10-151-1/+3
* Load an IDT with NULL limitStefan Reinauer2011-10-132-1/+15
* Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=EOskar Enoksson2011-10-111-3/+16
* Add AMD Family 10h PH-E0 supportQingPei Wang2011-09-243-0/+167
* Miscellaneous AMD F14 warning fixesefdesign982011-09-121-0/+4
* Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi2011-09-092-0/+28
* AMD F14 Rev C0 updateKerry She2011-09-071-0/+1
* Update AMD F14 Agesa to support Rev C0 cpusefdesign982011-08-061-1/+6
* cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui2011-08-044-3/+823
* Add SSE3 dependent codeefdesign982011-07-221-1/+32
* Update AMD SR5650 and SB700efdesign982011-07-221-0/+1
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