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* Some more #if cleanupPatrick Georgi2012-05-084-6/+6
* Clean up #ifsPatrick Georgi2012-05-0816-66/+66
* Fix register corruption during Intel Microcode updateStefan Reinauer2012-05-031-1/+1
* Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer2012-05-021-0/+2
* Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer2012-05-011-0/+2
* Move VSA support from x86 to GeodePatrick Georgi2012-05-012-0/+8
* Make geode_lx use the vsa from blobs repositoryPatrick Georgi2012-05-011-1/+3
* Fix up Sandybridge C state generation codeStefan Reinauer2012-04-301-6/+12
* Rework ACPI CST table generationStefan Reinauer2012-04-302-3/+3
* Move top level pc80 directory to drivers/Stefan Reinauer2012-04-271-1/+1
* microcode: print date of microcode and unify outputStefan Reinauer2012-04-261-3/+5
* Revamp Intel microcode update codeStefan Reinauer2012-04-262-118/+50
* Replace cache control magic numbers with symbolsPatrick Georgi2012-04-2510-46/+57
* amd: Fix unused variable warningVikram Narayanan2012-04-221-1/+2
* Revert wbind added to the reset_vectorMarc Jones2012-04-201-1/+0
* S3 code in coreboot public folder.zbao2012-04-166-54/+453
* S3 code in vendorcode folder.zbao2012-04-121-0/+1
* Remove obsolete empy macro definitionRon Minnich2012-04-111-2/+0
* Fixes and Sandybridge support for lapic cpu initStefan Reinauer2012-04-061-4/+11
* Fix support for RAM-less multi-processor initKyösti Mälkki2012-04-061-0/+1
* Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer2012-04-061-0/+8
* Cache 8MB flash instead of 4MBStefan Reinauer2012-04-061-25/+21
* Fix timer frequency detection on SandybridgeStefan Reinauer2012-04-051-12/+36
* Invalidate cache before first jumpStefan Reinauer2012-04-051-0/+1
* Update documentation in smmrelocate.S to mention TSEGStefan Reinauer2012-04-051-8/+11
* Add support for Intel Sandybridge CPUStefan Reinauer2012-04-0519-3/+2446
* Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer2012-04-045-3/+427
* Add support for Intel Turbo Boost featureStefan Reinauer2012-04-032-0/+91
* Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki2012-04-022-1/+18
* S3 code whitespaces changes.zbao2012-04-021-20/+20
* Whitespace fixesPatrick Georgi2012-03-312-2/+2
* Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki2012-03-311-13/+45
* Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki2012-03-311-13/+134
* Intel cpus: improve CPU compatibility of new CARKyösti Mälkki2012-03-311-1/+30
* Add support for RAM-less multi-processor initKyösti Mälkki2012-03-311-0/+6
* Intel cpus: apply some good programming practices in new CARKyösti Mälkki2012-03-311-24/+15
* Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki2012-03-311-3/+6
* Intel cpus: copy model_6ex CAR codeKyösti Mälkki2012-03-311-0/+268
* Make MTRR min hole alignment 64MBDuncan Laurie2012-03-301-3/+6
* Fix MB calculation in the reporting of the MTRR holeDuncan Laurie2012-03-301-1/+1
* MTRR: add alternate allocation method for odd memory mapsDuncan Laurie2012-03-301-7/+45
* Add Kconfig options to enable TSEG and set a sizeDuncan Laurie2012-03-301-0/+8
* drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer2012-03-302-7/+1
* Add an option to keep the ROM cached after romstageStefan Reinauer2012-03-304-3/+19
* Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki2012-03-251-4/+25
* Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki2012-03-251-13/+9
* Intel cpus: Include CAR from socketKyösti Mälkki2012-03-173-1/+2
* Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki2012-03-162-4/+7
* Fix AMD Agesa leaking KconfigKyösti Mälkki2012-03-162-8/+5
* ROMCC boards have no XIP limitPatrick Georgi2012-03-161-0/+1
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