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* AMD k8 fam10: Refactor S3 recoveryKyösti Mälkki2016-06-291-20/+16
* intel/haswell: No need for ACPI S3 resume backupKyösti Mälkki2016-06-291-7/+0
* intel romstage: Use run_ramstage()Kyösti Mälkki2016-06-291-2/+2
* region: Add writeat and eraseat supportAntonello Dettori2016-06-241-1/+1
* ACPI S3: Add common recovery codeKyösti Mälkki2016-06-221-17/+2
* ACPI S3: Move SMP trampoline recoveryKyösti Mälkki2016-06-221-14/+24
* Ignore RAMTOP for MTRRsKyösti Mälkki2016-06-2212-18/+18
* intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-222-2/+9
* intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-222-2/+9
* intel cache-as-ram: Fix comment about MTRRsKyösti Mälkki2016-06-223-6/+6
* intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-215-2/+12
* intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-214-3/+11
* intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-216-2/+13
* amd/fam_10h-fam_15h: allow building without microcode updatesArthur Heymans2016-06-201-1/+1
* amd/geode: Fix comment about ACPI S3Kyösti Mälkki2016-06-202-6/+2
* VIA C7 NANO: Fix early MTRR settingKyösti Mälkki2016-06-201-3/+3
* intel: Fix romstage main() with asmlinkageKyösti Mälkki2016-06-181-0/+7
* intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki2016-06-182-2/+2
* intel cache_as_ram: Fix typo in commentKyösti Mälkki2016-06-181-1/+1
* intel/model_206ax: Move platform specific definesKyösti Mälkki2016-06-171-1/+1
* Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki2016-06-173-0/+3
* Fix some cbmem.h includesKyösti Mälkki2016-06-173-3/+1
* AGESA vendorcode: Build a common amdlibKyösti Mälkki2016-05-181-0/+29
* intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer2016-05-171-2/+2
* AGESA f12: Build as libagesa.aKyösti Mälkki2016-05-121-282/+0
* AGESA f16kb: Build as libagesa.aKyösti Mälkki2016-05-121-414/+0
* drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy2016-05-092-0/+2
* cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZEAaron Durbin2016-05-061-0/+11
* {cpu,soc}/intel: remove unused smm_init() functionAaron Durbin2016-05-061-9/+0
* cpu/x86/mp_init: reduce exposure of internal implementationAaron Durbin2016-05-061-3/+75
* cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin2016-05-063-197/+88
* cpu/x86: combine multiprocessor and SMM initializationAaron Durbin2016-05-041-0/+242
* cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin2016-05-045-8/+1
* cpu/x86/smm_module_loader: always build with SMM module supportAaron Durbin2016-05-041-2/+1
* cpu/x86/mp_init: remove unused callback argumentsAaron Durbin2016-05-022-9/+9
* soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov2016-04-281-0/+1
* cpu/x86/tsc: Compile TSC timer for postcar as wellAndrey Petrov2016-04-111-0/+1
* cpu/x86/tsc: remove conditional compilationAaron Durbin2016-04-111-8/+8
* cpu/x86/tsc: compile same code for all stagesAaron Durbin2016-04-111-16/+8
* cpu/x86/tsc: prepare for CAR_GLOBAL in delay_tsc.cAaron Durbin2016-04-111-10/+19
* src/cpu/x86: remove TSC_CALIBRATE_WITH_IOAaron Durbin2016-04-112-64/+0
* am335x: Add some code for manipulating GPIOsGabe Black2016-04-103-0/+160
* am335x: Add data structures for the clock module registersGabe Black2016-04-101-0/+234
* src/: Fix lint style-labels warningsMartin Roth2016-03-312-2/+2
* arch/x86: introduce postcar stage/phaseAaron Durbin2016-03-231-0/+1
* mtrr: Define a function for obtaining free var mtrrFurquan Shaikh2016-03-181-0/+24
* cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov2016-03-161-0/+1
* cpu/x86/mtrr: remove early_mtrr_* functionsAaron Durbin2016-03-161-77/+0
* cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin2016-03-161-8/+0
* cpu/via/c7: Don't manually include udelay_io.cStefan Reinauer2016-03-101-1/+3
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