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* src/device/device.c: Don't use device_t in ramstageElyes HAOUAS2018-09-191-3/+3
| | | | | | | | | | | Use of device_t has been abandoned in ramstage. Change-Id: I3d1bdefd00c91a98116ede5dc03c3ce253d1f0ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* src/{device,drivers}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-091-1/+1
| | | | | | | | Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* device: Always build device_simple.c for less code duplicationNico Huber2018-05-241-2/+0
| | | | | | | | | | Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/device: Get rid of device_tElyes HAOUAS2018-05-221-6/+8
| | | | | | | | | | | | Use of device_t has been abandoned in ramstage. The function prototype for "struct device *add_cpu_device" is already correct and doesn't need to be fixed. Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS2018-05-091-1/+1
| | | | | | | | Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* device: constify some variablesLubomir Rintel2018-04-301-11/+11
| | | | | | | | | Change-Id: I6830a65bc9cea2907f4209bb97a53ccebcbf248d Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Enable ebda library for romstage and postcarSubrata Banik2017-09-221-2/+7
| | | | | | | | | | | | | This patch provides a kconfig option as EARLY_EBDA_INIT to ensures user can make use of EBDA library even during early boot stages like romstage, postcar. Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src/device: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-281-5/+5
| | | | | | | | | | | | Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* devtree: Drop unused parameter show_devs_tree() callKyösti Mälkki2017-02-061-1/+1
| | | | | | | | | Change-Id: I14c044bb32713ef4133bce8a8238a2bc200c4959 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18085 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* src/device: Update license headersMartin Roth2016-04-131-4/+10
| | | | | | | | | | | | Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I5e5180ec4303a121609b4acffb284daea6b08379 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14325 Reviewed-by: Myles Watson <mylesgw@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* device/device.c: remove warning for missing apic read resourcesMartin Roth2015-11-191-2/+3
| | | | | | | | | | | | We have had the "APIC: 00 missing read_resources" messages for many years. It's obviously not an error, and also doesn't cause boot failures. Therefore, remove the message. Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12471 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* device: Stop and output time in `scan_bus()`Paul Menzel2015-10-271-0/+6
| | | | | | | | | | | | | Output how long it took to scan a bus. Note, that the function `scan_bus()` is called recursively. Change-Id: I6335e10db783f092ea18d3a1c79f93135bee5826 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12103 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* resource: Refactor IORESOURCE flags useKyösti Mälkki2015-06-101-29/+34
| | | | | | | | | | | | The type of a resource is really an enumeration but our implementation is as a bitmask. Compare all relevant bits and remove the shadowed declarations of IORESOURCE bits. Change-Id: I7f605d72ea702eb4fa6019ca1297f98d240c4f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8891 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* PCI subsystem: Drop PCI_64BIT_PREF_MEM optionKyösti Mälkki2015-06-101-29/+6
| | | | | | | | | | | | | | | | | No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* device/device.c: Improve output in `init_dev()`Paul Menzel2015-06-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 05294292 (device tree: track init times) there are two lines printed for each init() call of a device, when `HAVE_MONOTONIC_TIMER` is selected. […] CPU_CLUSTER: 0 init 12708 usecs DOMAIN: 0000 init DOMAIN: 0000 init 1 usecs PCI: 00:00.0 init Northbridge init PCI: 00:00.0 init 2 usecs PCI: 00:01.0 init PCI: 00:01.0 init 1 usecs PCI: 00:01.1 init PCI: 00:01.1 init 1 usecs PCI: 00:11.0 init PCI: 00:11.0 init 1 usecs PCI: 00:14.0 init PCI: 00:14.0 init 1 usecs PCI: 00:14.3 init SB800 - Late.c - lpc_init - Start. RTC Init RTC: coreboot checksum invalid SB800 - Late.c - lpc_init - End. […] Improve the output by changing the wording to. %s init ...\n init() %s init finished in %ld usecs\n Note, that `%s init ... done in %ld usecs` is not possible as the function `init()` can also print messages. Change-Id: I7132cd650911dba680f060d6073a5a09c879b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* devicetree: Change scan_bus() prototype in device opsKyösti Mälkki2015-06-041-11/+5
| | | | | | | | | | | | | | The input/output value max is no longer used for tracking the bus enumeration sequence, everything is handled in the context of devicetree bus objects. Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8541 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* devicetree: Single scan_bridges()Kyösti Mälkki2015-06-041-4/+17
| | | | | | | | | Change-Id: Ifd277992a69a4182e2fac92aaf746abe4fec2a1b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8540 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* resource: Adjust memory resources high earlierKyösti Mälkki2015-05-051-15/+4
| | | | | | | | | | Do this to avoid reporting incorrect resource window in the logs. Change-Id: Icb7978deeb54f0ec6c29473ce9034fe44b6d7602 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* resource: Enhance resource reportingKyösti Mälkki2015-05-051-35/+35
| | | | | | | | | | Remove some redundancy in both source code and console output. Change-Id: I32350966de7af30b3ca4ac747fe3bf623ea9484b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* resource: Report correct secondary resource windowKyösti Mälkki2015-05-051-0/+1
| | | | | | | | | | | | Once a bridge window resource is allocated, it becomes the base and limit for any resource on the secondary bus. Upper limit was incorrectly reported in the log while assigning secondary resources. Change-Id: I69f0a02aae6d13f77aaa2dace924b8970b23edad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* device: convert to stopwatch APIAaron Durbin2015-03-211-6/+3
| | | | | | | | | | | | | | | | | | | | | Instead of open coding the monotonic timers use the stopwatch abstraction. BUG=None BRANCH=None TEST=Booted and noted timings work as expected. Built with software_i2c and no compilation failures. Change-Id: Ie5ecdd5bc764c1ab8ba4a923e65a1666aacd22f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7bffb5aeb41e9b88cd2c99edd6abc38f1dc90af Original-Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219495 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8817 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* doxygen fixes: fix parameter names to match the functionsMartin Roth2015-01-061-1/+1
| | | | | | | | | | | | | The doxygen parameter names in the comments no longer matched the functions they were attached to. Doxygen complains about extra parameter comments and uncommented parameters in the functions. Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8101 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* PCI: Guard pci.h with CONFIG_PCIKyösti Mälkki2014-02-121-1/+1
| | | | | | | | | | | | Adding PCI functions for romstage in pci.h breaks ARMv7 build without this. Also fix two related includes to use pci_def.h instead. Change-Id: I5291eaf6ddf5a584f50af29cf791d2ca4d9caa71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5199 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
* Log device path during resource allocationDuncan Laurie2013-12-121-0/+4
| | | | | | | | | | | | | | | | Systems are hanging in dev_configure() without a log to indicate which device is being processed. Add some logging points to save the device path before talking to the device so we can narrow in on which device is the problem. Change-Id: I3751c19a1ea68cdccbc33e4f6b2eeddd1bd9f2e4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61296 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4349 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Clean up POST codes for Boot State machineDuncan Laurie2013-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that there is a clearly defined boot state machine we can add some useful post codes to indicate the current point in the state machine by having it log a post code before the execution of each state. This removes the currently defined POST codes that were used by hardwaremain in favor of a new contiguous range that are defined for each boot state. The reason for this is that the existing codes are mostly used to indicate when something is done, which is confusing for actual debug because POST code debugging relies on knowing what is about to happen (to know what may be at fault) rather than what has just finished. One additonal change is added during device init step as this step often does the bulk of the work, and frequently logs POST codes itself. Therefore in order to keep better track of what device is being initialized POST_BS_DEV_INIT is logged before each device is initialized. interrupted boot with reset button and gathered the eventlog. Mosys has been extended to decode the well-known POST codes: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: Ida1e1129d274d28cbe8e49e4a01483e335a03d96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58106 Reviewed-on: http://review.coreboot.org/4231 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Log device path into CMOS during probe stagesDuncan Laurie2013-11-261-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the most common hangs during coreboot execution is during ramstage device init steps. Currently there are a set of (somewhat misleading) post codes during this phase which give some indication as to where execution stopped, but it provides no information on what device was actually being initialized at that point. This uses the new CMOS "extra" log banks to store the encoded device path of the device that is about to be touched by coreboot. This way if the system hangs when talking to the device there will be some indication where to investigate next. interrupted boot with reset button and gathered the eventlog after several test runs: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58105 Reviewed-on: http://review.coreboot.org/4230 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Add new finalize functions for devices and chipsMarc Jones2013-11-081-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | Many chipset devices require additional configuration after device init. It is not uncommmon for a device early in the devicetree list to need to change a setting after a device later in the tree does PCI init. A final function call has been added to device ops to handle this case. It is called prior to coreboot table setup. Another problem that is often seen is that the chipset or mainboard need to do some final cleanup just before loading the OS. The chip finalize has been added for this case. It is call after all coreboot tables are setup and the payload is ready to be called. Similar functionality could be implemented with the hardwaremain states, but those don't fit well in the device tree function pointer structure and should be used sparingly. Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4012 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* device: Fix spellingMartin Roth2013-07-101-7/+7
| | | | | | | | | Change-Id: I53a40d114aa2da76398c5b97443d4096809dcf36 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3730 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* device tree: track init timesAaron Durbin2013-05-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of a monotonic timer it is possible to track the individual times of each device's init() call. Add this ability behind a HAVE_MONOTONIC_TIMER option. Example log messages: Root Device init 5 usecs CPU_CLUSTER: 0 init 66004 usecs PCI: 00:00.0 init 1020 usecs PCI: 00:02.0 init 456941 usecs PCI: 00:13.0 init 3 usecs PCI: 00:14.0 init 3 usecs PCI: 00:15.0 init 92 usecs PCI: 00:15.1 init 37 usecs PCI: 00:15.2 init 36 usecs PCI: 00:15.3 init 35 usecs PCI: 00:15.4 init 35 usecs PCI: 00:15.5 init 36 usecs PCI: 00:15.6 init 35 usecs PCI: 00:16.0 init 3666 usecs PCI: 00:17.0 init 63 usecs PCI: 00:1b.0 init 3 usecs PCI: 00:1c.0 init 89 usecs PCI: 00:1c.1 init 15 usecs PCI: 00:1c.2 init 15 usecs PCI: 00:1c.3 init 15 usecs PCI: 00:1c.4 init 15 usecs PCI: 00:1c.5 init 16 usecs PCI: 00:1d.0 init 4 usecs PCI: 00:1f.0 init 495 usecs PCI: 00:1f.2 init 29 usecs PCI: 00:1f.3 init 4 usecs PCI: 00:1f.6 init 4 usecs Change-Id: Ibe499848432c7ab20166ab10d6dfb07db03eab01 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3162 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
* sconfig: rename pci_domain -> domainStefan Reinauer2013-02-141-4/+4
| | | | | | | | | | | | | | The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Rename devices -> deviceStefan Reinauer2012-11-301-0/+1157
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 07:44:33 +0000