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* device/i2c_bus: Constify i2c_busdev and i2c_linkMatt DeVillier2022-04-011-1/+1
| | | | | | | | | Change-Id: If795087ecdaea24ad7834dcc6d5bf6a72f2aea8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* device/pci_device.c: Return if the scan parameter is invalidArthur Heymans2022-03-301-0/+2
| | | | | | | | | | | Clang is unhappy about codepath of an invalid parameter because variables remain unset. Change-Id: I1ba392a48cf3f81a29d9645e5cf220b122d588af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* device/pciexp_device: Set resources for pciexp_hotplug_dummy_opsJohn Su2022-03-281-0/+1
| | | | | | | | | | | | | | | | | | | | Without setting the set_resources field for pciexp_hotplug_dummy_ops, we will get an error during pciexp_hotplug_dummy. [ERROR] NONE missing set_resources Because the set_resources field is considered mandatory, explicitly set it as no-op noop_set_resources. BUG=b:220639445 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ifee7479c69cf16025dbd4e3924056ed7f8e253cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63101 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* i2c: Add configurable I2C transfer timeoutJes Klinke2022-03-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* src: Make PCI ID define names shorterFelix Singer2022-03-071-1/+1
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* device/pci_device.c: Improve pci_bridge_route() readabilityArthur Heymans2022-03-021-13/+13
| | | | | | | | | | | | | Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate variables and PCI config writes to improve the readability. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/pci_device: Fix PCIe bridge detectionNico Huber2022-02-281-0/+3
| | | | | | | | | | | | | | | | | | PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(), it's our virtual `domain` device. Expecting a PCI device above bus 0 resulted in undefined behavior for all boards with PCI. Only boards with a PCI device 00:00.0 that looked like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake). Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171 Signed-off-by: Nico Huber <nico.h@gmx.de> Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe) Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Get rid of CONFIG_AZALIA_MAX_CODECSElyes Haouas2022-02-222-14/+5
| | | | | | | | | | | | | Get rid of Kconfig symbol introduced at commit 5d31dfa8 High Definition Audio Specification Revision 1.0a says, there are 15 SDIWAKE bits. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Add support for PCIe Resizable BARsTim Wawrzynczak2022-02-162-3/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability. When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range. This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig. BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* device: Add pciexp_find_next_extended_cap functionTim Wawrzynczak2022-02-101-11/+21
| | | | | | | | | | | | | | | | | | | Some PCIe devices have extended capability lists that contain multiples instances of the same capability. This patch provides a function similar to pciexp_find_extended_cap that can be used to search through multiple instances of the same capability by returning the offset of the next extended capability of the given type following the passed-in offset. The base functionality of searching for a given capability from an offset is extracted to a local helper function and both pciexp_find_extended_cap and pciexp_find_next_extended_cap use this helper. Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* device/dram/ddr2.c: Fix log messagesElyes HAOUAS2022-02-081-5/+4
| | | | | | | | | | Change 'printk(BIOS_WARNING, "ERROR:' to printk(BIOS_ERR, "'. Change-Id: Id25bdb1e6b6d7085eff9c2be8263223a91dff061 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-075-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* src: Add missing 'void' in function definitionElyes HAOUAS2022-01-261-1/+1
| | | | | | | | | Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device: constify pciexp_find_extended_cap()Tim Wawrzynczak2022-01-241-1/+1
| | | | | | | | | | | The object pointed to by the struct device * argument is not modified, therefore it can be made const. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I300d2a59eb0513ddd08d4f1d2a3c6eb829e3f836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* oprom/yabel/io.c: Fix building for ENV_X86_64Arthur Heymans2022-01-171-2/+2
| | | | | | | | | | | Unknown if yabel works for X86_64 but now it builds. Change-Id: Iacdb9fde91a992b5010120f5824383ca4aebdd1a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* oprom/realmode/x86.c: Fix building for ENV_X86_64Arthur Heymans2022-01-171-2/+8
| | | | | | | | | | | Not tested on hardware. Change-Id: I8ce8d56da326aeff5ff9b400ded02d4309372519 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/pci_device.c: Make sure the PCI bus has a deviceArthur Heymans2022-01-121-0/+3
| | | | | | | | | | | | | | Some SOC add PCI root busses structs at runtime without adding a device struct to the bus because pci_scan_bus does it. An example would be xeon_sp which has multiple root busses. TEST: ocp/deltalake boots again. Change-Id: I81d9c94652e34dbf9e8cec64fc34ef0042563037 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* device/dram/lpddr4.c: Remove unused <string.h>Elyes HAOUAS2022-01-051-1/+0
| | | | | | | | Change-Id: Iba3135178f2d6021702971e4d887e9b4f8afeb76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* pci_device.c: Don't guard `pci_dev_disable_bus_master()`Angel Pons2022-01-011-5/+5
| | | | | | | | | | | | The `pci_dev_disable_bus_master()` function doesn't need to be guarded with `CONFIG(PC80_SYSTEM)`, so move it out of the guard. Change-Id: I813e0f72c3c624c73ab9ecbe7512359608ace927 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* device: Make pciexp_get_ltr_max_latencies a public functionTim Wawrzynczak2021-12-221-1/+1
| | | | | | | | | | | | | | | | Some device drivers may need to get access to the LTR values for their respective devices, therefore export this function instead of marking it static. BUG=b:204343849 Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* device/pci_device.c: Scan only one device for PCIeJianjun Wang2021-11-291-0/+27
| | | | | | | | | | | | | Only scan one device if it's a PCIe downstream port. A PCIe downstream port normally leads to a link with only device 0 on it. As an optimization, scan only for device 0 in that case. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* device/pci_rom: Add vga_oprom_preloadRaul E Rangel2021-11-151-0/+15
| | | | | | | | | | | | | | | This method will allow preloading the VGA_BIOS_FILE. By preloading the file, into cbfs_cache we reduce boot time. In the future we can also add support for loading the second VGA_BIOS_FILE and the DGPU VGA_BIOS_FILE. BUG=b:179699789 TEST=Boot guybrush to OS and verify 12 ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* device/azalia_device: Drop unused function parameterAngel Pons2021-11-111-2/+2
| | | | | | | | | | | The `dev` parameter of the `azalia_codecs_init()` function is not used. Remove it, and update all call sites accordingly. Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59119 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/azalia_device: Adapt and export `codec_init()`Angel Pons2021-11-111-3/+3
| | | | | | | | | | | | | | | | Make the `codec_init()` function non-static so that it can be used in other places. Rename it to `azalia_codec_init()` for consistency with the other functions of the API. Also, update the function's signature to make it more flexible. Remove the unused `dev` parameter and allow callers to pass the verb table to use. Update the original call site to preserve behavior. Change-Id: I5343796242065b5fedc78cd95bcf010c9e2623dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59117 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* azalia_device: Report if codec verb loading failedAngel Pons2021-11-111-2/+5
| | | | | | | | | | | Handle the return value of `azalia_program_verb_table()` and print different messages accordingly. Change-Id: I99e9e1416217c5e67c529944736affb31f9c7d2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59115 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/azalia_device: Export `codecs_init()`Angel Pons2021-11-111-2/+2
| | | | | | | | | | | | | Make the `codecs_init()` function non-static so that it can be used in other places. Rename it to `azalia_codecs_init()` to avoid name clashes with static definitions in southbridge code (which will be removed in subsequent commits). Change-Id: I080a73102b0c4f9f8a283cd93bba9b3b23169be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik2021-11-113-9/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-103-18/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* treewide: Replace bad uses of `find_resource`Angel Pons2021-11-041-1/+1
| | | | | | | | | | | | | | | The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
* src/acpi to src/lib: Fix spelling errorsMartin Roth2021-10-059-9/+9
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Drop unused function `dev_find_matching_device_on_bus`Furquan Shaikh2021-09-241-13/+0
| | | | | | | | | | | | With use of device pointers, `dev_find_matching_device_on_bus()` is now unused and hence this change drops the function. Change-Id: I30fcb2d9932d770ca614cceffb15646ce8256465 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/dram/spd.c: Add more manufacturer ID codesJingleHsuWiwynn2021-09-201-0/+3
| | | | | | | | | | | | | | Add manufacturer ID codes for Hynix, Samsung and Micron. Tested=On OCP Crater Lake, dmidecode -t 17 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I0b4bbc46d3bfd9e9534cdd59f90cbdc150f29542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daocheng Bu <daocheng.bu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/mmio: Make buffer_to_fifo32() take a const bufferJulius Werner2021-09-201-2/+2
| | | | | | | | | | | | | The input buffer to the buffer_to_fifo family of functions is only read, so it can be a const pointer. (Also, remove the MIPS check in libpayload for these functions... the MIPS architecture has been removed a while ago.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* device/dram: Add addtional LPDDR4 speed gradesRob Barnes2021-09-131-7/+37
| | | | | | | | | | | | | | | | | | | Add additonal LPDDR4 speed grades. This is needed because the limited set has casued confusion when the reported speed did not match expectations. There does not seem to be a definitive list of LPDDR4 speed grades, so this list is derieved from JEDEC 209-4C and a survey of commonly used LPDDR4 speed grades. BUG=b:194184950 TEST=Boot, dmidecode -t 17 reports correct speed BRANCH=None Change-Id: Ie7706fd4ad5a7df68c07b8ca43261429ba140c61 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
* device/mipi: Move to drivers/mipiJulius Werner2021-08-2617-2380/+1
| | | | | | | | | | | | | | Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner2021-08-203-0/+38
| | | | | | | | | | | | | | | | | | | | | | This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device_util.c: Replace `memcpy()` with `strcpy()`Angel Pons2021-08-191-3/+3
| | | | | | | | | | | Use `strcpy()` instead of `memcpy()` to copy string literals. Change-Id: I8ebf591e3348d992739ed7cc2e4015aa650f115a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner2021-08-1816-1/+2342
| | | | | | | | | | | | | | | | | | | | | | All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* device/pci_rom: Make ON_DEVICE_ROM_LOAD condition truthyRaul E Rangel2021-07-201-5/+5
| | | | | | | | | | | | | Truthy conditions are easier to reason about. BUG=none TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I229c3e90f5122d6191b28f9b4b6de79ac2fcb627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* device/pci_rom: Convert #if to C codeRaul E Rangel2021-07-201-3/+1
| | | | | | | | | | | | | No reason to use the preprocessor for this. BUG=none TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I920dfa2d27c2eb27e8bc50c615ccd13601610fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* lib/cbfs,device/pci_rom: Move cbfs_boot_map_optionrom and modernizeRaul E Rangel2021-07-201-0/+19
| | | | | | | | | | | | | | | These methods are oprom specific. Move them out of CBFS. I also deleted the tohex methods and replaced them with snprintf. BUG=b:179699789 TEST=Boot guybrush and see oprom still loads Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPCMartin Roth2021-07-142-14/+0
| | | | | | | | | | | | | | | | The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. The previous patch removes them from sconfig, so now they aren't needed in coreboot. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Reflow strings in printk statementsAngel Pons2021-07-053-26/+25
| | | | | | | | | | | | | To ease finding some log messages, reflow their strings to use one line. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/resource_allocator_v4: Only highlight log message with ===Paul Menzel2021-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | Currently, four instead of three = are used in one log message. Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === As the ending mark is `===` change it to `===` in the beginning. Done reading resources. === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56045 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Clean up resource utility function signaturesKyösti Mälkki2021-07-011-4/+4
| | | | | | | | | | | | Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_device.c: Reuse `irq` variableAngel Pons2021-07-011-3/+2
| | | | | | | | | | | The `irq` variable has the same value as `pIntAtoD[line - 1]`. Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* device/pci_device.c: Drop redundant guardAngel Pons2021-06-301-2/+0
| | | | | | | | | | | This guard is nested inside an identical guard already. Change-Id: I2b315ee6620865429097041035ad493ddcc51884 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* src/device/dram: Add terminating new lines to printk stringsNikolai Vyssotski2021-06-282-2/+2
| | | | | | | | | | | BUG=b:184124605 TEST=check serial log Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I521a2541e23d047e255b0cc8068ad63dfaf70bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* device: Add helper function devfn_disable()Subrata Banik2021-06-171-0/+7
| | | | | | | | | | | | devfn_disable() function is used to disable a device based on given bus, device function number. This function checks if the device is at enable state and disables the device. Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/pnp: Always provide `pnp_unset_and_set_config`Angel Pons2021-06-101-0/+9
| | | | | | | | | | | | | | The `pnp_unset_and_set_config` function was only available when building with `ENV_PNP_SIMPLE_DEVICE` set. Add the complementary definition using device pointers, for the sake of completeness. Change-Id: I2a21e635f41f3f786057500fa96a2b3116e30d76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-21 01:00:27 +0000