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* device/dram/spd.c: Add more manufacturer ID codesJingleHsuWiwynn2021-09-201-0/+3
| | | | | | | | | | | | | | Add manufacturer ID codes for Hynix, Samsung and Micron. Tested=On OCP Crater Lake, dmidecode -t 17 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I0b4bbc46d3bfd9e9534cdd59f90cbdc150f29542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daocheng Bu <daocheng.bu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/mmio: Make buffer_to_fifo32() take a const bufferJulius Werner2021-09-201-2/+2
| | | | | | | | | | | | | The input buffer to the buffer_to_fifo family of functions is only read, so it can be a const pointer. (Also, remove the MIPS check in libpayload for these functions... the MIPS architecture has been removed a while ago.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* device/dram: Add addtional LPDDR4 speed gradesRob Barnes2021-09-131-7/+37
| | | | | | | | | | | | | | | | | | | Add additonal LPDDR4 speed grades. This is needed because the limited set has casued confusion when the reported speed did not match expectations. There does not seem to be a definitive list of LPDDR4 speed grades, so this list is derieved from JEDEC 209-4C and a survey of commonly used LPDDR4 speed grades. BUG=b:194184950 TEST=Boot, dmidecode -t 17 reports correct speed BRANCH=None Change-Id: Ie7706fd4ad5a7df68c07b8ca43261429ba140c61 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
* device/mipi: Move to drivers/mipiJulius Werner2021-08-2617-2380/+1
| | | | | | | | | | | | | | Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner2021-08-203-0/+38
| | | | | | | | | | | | | | | | | | | | | | This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device_util.c: Replace `memcpy()` with `strcpy()`Angel Pons2021-08-191-3/+3
| | | | | | | | | | | Use `strcpy()` instead of `memcpy()` to copy string literals. Change-Id: I8ebf591e3348d992739ed7cc2e4015aa650f115a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner2021-08-1816-1/+2342
| | | | | | | | | | | | | | | | | | | | | | All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* device/pci_rom: Make ON_DEVICE_ROM_LOAD condition truthyRaul E Rangel2021-07-201-5/+5
| | | | | | | | | | | | | Truthy conditions are easier to reason about. BUG=none TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I229c3e90f5122d6191b28f9b4b6de79ac2fcb627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* device/pci_rom: Convert #if to C codeRaul E Rangel2021-07-201-3/+1
| | | | | | | | | | | | | No reason to use the preprocessor for this. BUG=none TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I920dfa2d27c2eb27e8bc50c615ccd13601610fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* lib/cbfs,device/pci_rom: Move cbfs_boot_map_optionrom and modernizeRaul E Rangel2021-07-201-0/+19
| | | | | | | | | | | | | | | These methods are oprom specific. Move them out of CBFS. I also deleted the tohex methods and replaced them with snprintf. BUG=b:179699789 TEST=Boot guybrush and see oprom still loads Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPCMartin Roth2021-07-142-14/+0
| | | | | | | | | | | | | | | | The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. The previous patch removes them from sconfig, so now they aren't needed in coreboot. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Reflow strings in printk statementsAngel Pons2021-07-053-26/+25
| | | | | | | | | | | | | To ease finding some log messages, reflow their strings to use one line. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/resource_allocator_v4: Only highlight log message with ===Paul Menzel2021-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | Currently, four instead of three = are used in one log message. Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === As the ending mark is `===` change it to `===` in the beginning. Done reading resources. === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56045 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Clean up resource utility function signaturesKyösti Mälkki2021-07-011-4/+4
| | | | | | | | | | | | Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_device.c: Reuse `irq` variableAngel Pons2021-07-011-3/+2
| | | | | | | | | | | The `irq` variable has the same value as `pIntAtoD[line - 1]`. Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* device/pci_device.c: Drop redundant guardAngel Pons2021-06-301-2/+0
| | | | | | | | | | | This guard is nested inside an identical guard already. Change-Id: I2b315ee6620865429097041035ad493ddcc51884 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* src/device/dram: Add terminating new lines to printk stringsNikolai Vyssotski2021-06-282-2/+2
| | | | | | | | | | | BUG=b:184124605 TEST=check serial log Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I521a2541e23d047e255b0cc8068ad63dfaf70bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* device: Add helper function devfn_disable()Subrata Banik2021-06-171-0/+7
| | | | | | | | | | | | devfn_disable() function is used to disable a device based on given bus, device function number. This function checks if the device is at enable state and disables the device. Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/pnp: Always provide `pnp_unset_and_set_config`Angel Pons2021-06-101-0/+9
| | | | | | | | | | | | | | The `pnp_unset_and_set_config` function was only available when building with `ENV_PNP_SIMPLE_DEVICE` set. Add the complementary definition using device pointers, for the sake of completeness. Change-Id: I2a21e635f41f3f786057500fa96a2b3116e30d76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* device/dram: Add LPDDR4 utilitiesRob Barnes2021-06-092-2/+72
| | | | | | | | | | | | | | | | Add lpddr4.c utility file with lpddr4_speed_mhz_to_reported_mts. Fill in lpddr4_speeds using JDEC 209-4C table 210. LPDDR4 SPD decoding utilities are not included since there isn't a present need. BUG=b:184124605 TEST=Build and run on guybrush Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* device: Add helper function is_devfn_enabled()Subrata Banik2021-06-091-0/+6
| | | | | | | | | | | | | | is_devfn_enabled() function helps to check if a device is enabled based on given device function number. This function internally called is_dev_enabled() to check device state. Change-Id: I6aeba0da05b13b70155a991f69a6abf7eb48a78c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* device: Consider fw_config probing in `is_dev_enabled()`Furquan Shaikh2021-05-241-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of fw_config support in coreboot, it is possible for mainboards to control the state of a device (on/off) in ramstage using fw_config probe conditions. However, the device tree in immutable in all other stages and hence `is_dev_enabled()` does not really reflect the true state as in ramstage. This change adds a call to `fw_config_probe_dev()` in `is_dev_enabled()` when device tree is immutable (by checking DEVTREE_EARLY) to first check if device is disabled because of device probe conditions. If so, then it reports device as being disabled. Else, dev->enabled is used to report the device state. This allows early stages (bootblock, romstage) to use `is_dev_enabled()` to get the true state of the device by taking probe conditions into account and eliminates the need for each caller to perform their own separate probing. Change-Id: Ifede6775bda245cba199d3419aebd782dc690f2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54752 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/device.c: Print bus numbers in decimalAngel Pons2021-05-111-1/+1
| | | | | | | | | | For consistency with other log messages, print bus numbers in decimal. Change-Id: Ib08ae40fc67c5f8fafd760e8dbb729d6de34c2bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* device: Drop unused `uma_memory_{base,size}` globalsAngel Pons2021-05-101-6/+0
| | | | | | | | | | These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak2021-05-031-6/+3
| | | | | | | | | | | | | | | | | | | | | With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* device/azalia_device.c: Add option to lock down GCAPAngel Pons2021-04-192-0/+14
| | | | | | | | | | | | | | | On Intel 6-series PCHs, the GCAP register is R/WO (Read / Write Once), and needs to be written to after the HD Audio controller is taken out of reset. Add a Kconfig option to read and write back GCAP in order to lock it down. Follow-up commits will select this option when switching platforms to use common Azalia code, to preserve original behaviour. Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/Kconfig: Adapt PCIEXP_HOTPLUG_BUSESNico Huber2021-04-181-0/+2
| | | | | | | | | | | | | | | | | | The default of 32 buses per hotplug bridge is rather high. Especially for platforms that limit MMConf space to 64 buses: they run out of numbers if there is more than a single hotplug bridge. Lower the default to * 8 if MMConf is limited to 64 or less buses, * 16 if MMConf is limited to 128 or less buses. Change-Id: I06d522dd92ceea9f4798273b26f947a5333800c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52069 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Rename do_printk() to printk()Nico Huber2021-04-141-15/+15
| | | | | | | | | | | | | The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* device/i2c_bus.c: Correct code styleFrans Hendriks2021-04-061-8/+4
| | | | | | | | | | | | | | | | | device: Correct code style Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition. - Remove unnecessary newlines. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
* device/dram/ddr3: Drop unused MRS helpersAngel Pons2021-04-051-223/+0
| | | | | | | | | | These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* device/dram/ddr4.h: Align with DDR3 and DDR2Angel Pons2021-04-051-6/+6
| | | | | | | | | | | | Drop unnecessary typedefs and rename DDR4-specific definitions to avoid name clashes, as done for DDR3 in earlier commits. This allows including and using both DDR3 and DDR4 headers in the same compilation unit. Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons2021-04-051-10/+10
| | | | | | | | | | | To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/dram/ddr3: Get rid of useless typedefsAngel Pons2021-04-051-4/+4
| | | | | | | | | | | These typedefs are not necessary. Remove them, and rename some elements to avoid any confusion with other DRAM generations, such as DDR4. Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/azalia_device.c: Program beep verbsPatrick Rudolph2021-03-241-0/+2
| | | | | | | | Change-Id: I11b362d5e586194501de5dbd11f9c934a9d53940 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/azalia_device.c: Introduce AZALIA_MAX_CODECSAngel Pons2021-03-242-3/+12
| | | | | | | | | | | Add the AZALIA_MAX_CODECS Kconfig option and use it. Change-Id: Ibb10c2f2992257bc261e6cb35f11cc4b2d956054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* device/azalia_device.c: Correct STATESTS access widthAngel Pons2021-03-241-13/+13
| | | | | | | | | | | The HD Audio spec states that the STATESTS register is 16 bits wide. Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/azalia_device.c: Unify `wait_for_valid` timeoutsAngel Pons2021-03-241-8/+11
| | | | | | | | | | | | | | | | | | | | | | The timeout is never reached when the codec is functioning properly. Using a small timeout value can result in spurious errors with some codecs, e.g. a codec that is slow to respond but operates correctly. When a codec is non-operative, the timeout is only reached once per verb table, thus the impact on booting time is relatively small. So, use a reasonably long enough timeout to cover all possible cases. Remove the unconditional 25 µs delay and increase the timeout delay. The new value of 1 ms is the maximum of all existing implementations. Currently, the only boards using this code are AMD reference boards: - AMD Bilby - AMD Mandolin - AMD Padmelon Change-Id: Ia5e4829d404dcecdb9e7a377e896a319cb38531a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/azalia_device.c: Switch to stopwatchPatrick Rudolph2021-03-221-12/+16
| | | | | | | | | | | | Use timer.h helpers instead of open-coding timeout handling in polling loops. The 25-microsecond delay in `wait_for_valid` looks odd, and may be removed in subsequent commits. For now, preserve existing behavior. Change-Id: Id1227c6812618597c37408a7bf53bcbcae97374a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50789 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pciexp_device: Rewrite LTR configurationNico Huber2021-03-151-39/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was bugged by spurious "Failed to enable LTR" messages for years. Looking at the the current algorithm, it is flawed in multiple ways: * It looks like the author didn't know they implemented a recursive algorithm (pciexp_enable_ltr()) inside another recursive algorithm (pciexp_scan_bridge()). Thus, at every tree level, everything is run again for the whole sub- tree. * LTR is enabled no matter if `.set_ltr_max_latencies` is implemented or not. Leaving the endpoints' LTR settings at 0: They are told to always report zero tolerance. In theory, depending on the root-complex implementation, this may result in higher power consumption than without LTR messages. * `.set_ltr_max_latencies` is only considered for the direct parent of a device. Thus, even with it implemented, an endpoint below a (non-root) bridge may suffer from the 0 settings as described above. * Due to the double-recursive nature, LTR is enabled starting with the endpoints, then moving up the tree, while the PCIe spec tells us to do it in the exact opposite order. With the current implementation of pciexp_scan_bridge(), it is hard to hook anything in that runs for each device from top to bottom. So the proposed solution still adds some redundancy: First, for every device that uses pciexp_scan_bus(), we enable LTR if possible (see below). Then, when returning from the bus- scanning recursion, we enable LTR for every device and configure the maximum latencies (if supported). The latter runs again on all bridges, because it's hard to know if pciexp_scan_bus() was used for them. When to enable LTR: * For all devices that implement `.set_ltr_max_latencies`. * For all devices below a bridge that has it enabled already. Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pciexp_device.c: Remove CPP guardingArthur Heymans2021-03-142-10/+8
| | | | | | | | | | | | Let the linker do its job. This fixes building with !CONFIG_PCIEXP_HOTPLUG on some platforms. Change-Id: I46560722dcb5f1d902709e40b714ef092515b164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/amd/common/block/graphics/graphics: GOP: load VBIOSNikolai Vyssotski2021-03-131-1/+1
| | | | | | | | | | | | | | | | Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000) since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not set). Add Cezanne GFX PID. BUG=b:171234996 BRANCH=Zork Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 properNico Huber2021-03-121-4/+4
| | | | | | | | | | | | | | | | Replace the existing, odd looking, unordered definitions used for LTR configuration with the usual names used by upstream libpci. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Fixes: Code looked like UEFI copy-pasta. Header file was a mess. Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber2021-03-121-2/+2
| | | | | | | | | | | | | | Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/device.c: Rename .disable to .vga_disableArthur Heymans2021-02-241-2/+2
| | | | | | | | | | This makes it clear what this function pointer is used for. Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/dram: Move SPD manufacturer names out of arch/x86Patrick Rudolph2021-02-162-1/+38
| | | | | | | | | | | Move SPD manufacturer ID decoding to device/dram. Will be used by the following patch outside of SMBIOS scope as well. Change-Id: Iec175cd6ab1d20761da955785e4bc0e87ae02dbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`Paul Menzel2021-02-152-3/+3
| | | | | | | | | | | It’s good practice to put the unit into the name. Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/device: Remove unused <console/console.h>Elyes HAOUAS2021-02-151-1/+0
| | | | | | | | Change-Id: I30ed9661d8e84be49d362baafbb2bc624952c287 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50522 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/azalia_device: Add mainboard hook to program codecsAngel Pons2021-02-101-0/+6
| | | | | | | | | | | | | On some mainboards, codec configuration depends on settings that are only known at runtime, which is impossible to specify using one verb table. Add an optional `mainboard_azalia_program_runtime_verbs` hook where mainboards can program runtime-dependent codec verbs. Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* device/azalia_device: Add function to program a verb tableAngel Pons2021-02-101-10/+23
| | | | | | | | | | | | On some boards, Azalia configuration depends on config settings that are not known at compile-time. Expose a function to program a verb table, to be used in subsequent commits. Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* device/azalia_device.c: Correct print formatAngel Pons2021-02-101-1/+1
| | | | | | | | | | The type of `verb_size` is unsigned, thus use `%u` to print its value. Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 11:50:39 +0000