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* i2c/drivers/generic: Add support for including a rotation matrixSean Rhodes2024-02-212-0/+32
| | | | | | | | | | | | | | | | | | | | | The Rotation Matrix allows the specification of a 3x3 matrix representing the orientation of devices, such as accelerometers. Each value in the matrix can be one of -1, 0, or 1, indicating the transformation applied to the device's axes. It is expected by Linux and required for the OS to interpret the data from the device correctly. It is used by various drivers, mainly in `iio/accel`. It was tested on Ubuntu, by rotating the device and verifying the orientation was correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80179 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18100-0/+200
| | | | | | | | Change-Id: Ib27894f0f1e03501583fffb2c759b493d6a7b945 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80588 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drv/gfx/generic: Add Intel ACPI Backlight funcs for LCD devicesMatt DeVillier2024-02-141-0/+36
| | | | | | | | | | | | | | | | Normally this would be done by the Intel GMA driver, but we can't have two copies of the _DOD method, so generate the LCD backlight controls here to allow use of this driver instead of the default GMA panel definition. TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness controls functional. Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80061 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree; Remove unused <lib.h>Elyes Haouas2024-02-146-6/+0
| | | | | | | | | Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80433 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/gfx/generic: Add display type fieldMatt DeVillier2024-02-132-2/+24
| | | | | | | | | | | | | | | | | | | | Add an enum for the Display Type, which if set, can be used to generate the Device ID value dynamically when the addr field is not set. This will allow devicetree entries to specify the display type instead of a hex value for the address which requires referencing the ACPI spec to decode. For an internal panel connected to the first port on the graphics chip, currently an addr value of 0x80010400 is specified. Replacing the 'addr' field with the 'type' field and setting it to 'panel' will generate the same DID value. Change-Id: Id0294a14606b410a13fa22eeb240df9e409a7ca3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/uart/sifive.c: Fix divisor calculationMaximilian Brune2024-02-101-3/+10
| | | | | | | | | | | | | | | The divisor is calculated using the following formula: div = (frequency / baudrate) - 1; The current implementation however essentially calculates: div = (frequency / baudrate); Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I8a0898ce9016a70c0f91dc8a99fc1cf9e46d20c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79951 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* drivers/qemu: Drop redundant vga_io addition to ramstageAlper Nebi Yasak2024-02-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | While introducing driver support for QEMU Cirrus display device, commit 7905f9254ebc ("qemu: cirrus native video init") also explicitly adds VGA I/O functions into ramstage class when Bochs display driver support is enabled. Later, commit db7d04d1b753 ("qemu: Support textmode gfx init.") makes the related config option select CONFIG_VGA, which also adds the same file into ramstage class (among other things) in another Makefile. Doing this twice is unnecessary. Remove the addition based on the Bochs display driver's config option. Adding it based on CONFIG_VGA is clearer, and future patches will try to support a Bochs display without legacy VGA support on non-x86 architectures. Change-Id: Ib31344e242689682d74d8a83c97b6e8027641926 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80374 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* commonlib: Change GCD function to always use 64 bitsJulius Werner2024-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | It seems that we have some applications where we need to calculate a GCD in 64 bits. Now, we could instantiate the algorithm multiple times for different bit width combinations to be able to use the most efficient one for each problem... but considering that the function usually only gets called once per callsite per stage, and that software emulation of 64-bit division on 32-bit systems doesn't take *that* long either, we would probably usually be paying more time loading the second instance of the function than we save with faster divisions. So let's just make things easy and always do it in 64-bit and then nobody has to spend time thinking on which version to call. Change-Id: I028361444c4048a0d76ba4f80c7334a9d9983c87 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80319 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* drivers/pc80/tpm: probe for TPM family of a deviceSergii Dmytruk2024-02-071-25/+79
| | | | | | | | | | | | | At the moment this is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Later this TPM family will be returned to the caller. Change-Id: I23b85e6da0e02999704f3ec30412db0bdce2dd8a Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/wifi: Use depends instead of if in KconfigDavid Ruth2024-02-061-4/+1
| | | | | | | | | | | | | Cleanup to make the file follow the same convention after USE_MTCL was added and the depends structure was requested instead of the if guards. Signed-off-by: David Ruth <druth@google.com> Change-Id: I3604b394f999b28de4723337b3b6b4e21139c83b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/wifi: Add MTCL function to ACPI SSDTDavid Ruth2024-02-064-1/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related to MTCL * Add write_mtcl_aml function to convert the byte data into the format expected by the MTCL functionality in the Linux kernel. * Add validate_mtcl function to validate that the byte data read in from a file is in the expected format. * Add write_mtcl_function function to read a binary file called "wifi_mtcl".bin" from cbfs, then call validate_mtcl to verify that it is in an expected format, and if so write the aml via acpigen * Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Add config flag CONFIG_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.bin" * Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for MTK WiFi devices when USE_MTCL is enabled. * Add MediaTek VID to src/include/device/pci_ids.h. BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.bin blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth@chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80170 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* drivers/intel/fsp2_0: Remove unused function fsp_write_lineJeremy Compostella2024-02-052-15/+0
| | | | | | | | | | This is just a clean-up commit. Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* lib: Move IP checksum to commonlibJulius Werner2024-02-023-6/+5
| | | | | | | | | | | | | | | | | | | | | | This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* drivers/intel/gma: Add missing parentheses to brightness ACPIJonathon Hall2024-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d25277666829 ("tree: Replace And(a,b) with ASL 2.0 syntax") replaced two instances of `And(var, mask) == 0` with `var & mask == 0`. This expression needs parentheses - `(var & mask) == 0`. Without parentheses, it is always false, since the masks are nonzero (`var & (mask == 0)`; `var & 0`; `0`). This caused brightness changes on Intel GMA to take longer than normal since the status was never checked. The brightness would change immediately, but another brightness change could not occur until the first change timed out. This was most noticeable in KDE, which waits for the brightness change to complete before accepting another brightness up/down keypress. Tapping brightness up/down repeatedly would take much longer to reach max/min brightness due to many presses being ignored. It is noticeable in GNOME as well but less obvious. Tapping brightness up/down repeatedly would handle all keypresses, but the display's actual brightness would lag behind and skip some intermediate steps. I tested both Librem 13v2 and Librem 14, as far as I know this would apply to all systems configuring brightness with Intel GMA. Test: Verify brightness keys respond quickly again on Librem 13v2 / 14. Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80260 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* device/device.h: Rename busses for clarityArthur Heymans2024-01-3115-26/+26
| | | | | | | | | | This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-3176-76/+76
| | | | | | | | | | | | | | | | | | | | | | | Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/intel/common: Add lunarlake device IDsAppukuttan V K2024-01-261-0/+1
| | | | | | | | | | | | | | | Added Lunar Lake device IDs the device specific functions Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* drivers/mipi: Fine tune VFP, CLK and init code for IVO_T109NW41 panelRuihai Zhou2024-01-241-9/+9
| | | | | | | | | | | | | | | | | | 1. Adjust VFP and CLK to meet 60 +- 0.01 Hz 2. Fine tune init code for panel internal circuit Fixes: 520137f("drivers/mipi: Add support for IVO_T109NW41 panel") BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4d7c7bd4d79301fbb6d555117d190c358bceafcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80086 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* driver/parade to /driver/wwan: Rename Makefiles from .inc to .mkMartin Roth2024-01-2437-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cf3d2e2cd1b6ebe4e941ad64f27698379fef696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80080 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* driver/intel to /driver/ocp: Rename Makefiles from .inc to .mkMartin Roth2024-01-2426-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id47a5ef3c53f767d1e03c788e0022d05b21f5c28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* driver/i2c: Rename Makefiles from .inc to .mkMartin Roth2024-01-2433-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I358b878b97adfd9be156a5dd4a9cbaf9e81bca1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* driver/acpi to /driver/gfx: Rename Makefiles from .inc to .mkMartin Roth2024-01-2427-0/+0
| | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f299920eb7c6d6f8888cfe5e223ae03093a1d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80077 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* device: Add inline method to identify PATH_ROOTPatrick Rudolph2024-01-241-1/+1
| | | | | | | | | | | Add and use inline method to identify the root device. Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/mipi: Update init code for BOE_NV110WUM_L60Ruihai Zhou2024-01-141-5/+5
| | | | | | | | | | | | | | | | | | | | 1. Correct bank1 to bank0 2. Adjust CLK duty 3. Fix abnormal power off setting 4. Change VDDE power off frame from VGL to VGH Fixes: 0d50536("drivers/mipi: Add support for BOE_NV110WUM_L60 panel") BUG=b:319398058 TEST=boot Ciri with BOE_NV110WUM_L60 and see firmware screen Change-Id: I2f068ba0ec9dede3e3361b55c38a8eca8793905a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* drivers/smmstore/ramstage: use call_smmFelix Held2024-01-111-11/+4
| | | | | | | | | | | | | | | | | | Use call_smm instead of open-coding the same in inline assembly functionality in init_store. The local ebx variable is dropped, since call_smm takes a pointer to the argument instead of an integer, and the local eax variable is renamed to res to make the code a bit clearer, since the EAX register is used for both passing the command and subcommand to the APMC SMI handler and to get the return value from the handler. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* vc/google: Show different logos for different ChromeOS devicesShelley Chen2024-01-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for showing different logos on the ChromeOS firmware splash screen based on the device model (between Chromebook-Plus and regular ChromeOS devices like Chromebook and Chromebox). This allows OEMs to customize the branding on their devices. This patch also introduces three new Kconfigs: - CHROMEOS_FW_SPLASH_SCREEN - CHROMEOS_LOGO_PATH - CHROMEBOOK_PLUS_LOGO_PATH which allow users to enable the fw splash screen feature in the vendorcode. Previously, we were using the BMP_LOGO Kconfig in drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be located inside the architecture specific files. BUG=b:317880956 BRANCH=None TEST=emerge-rex coreboot chromeos-bootimage verify that FW splash screen appears Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79775 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* drivers/mipi: Add support for IVO_T109NW41 panelRuihai Zhou2024-01-093-0/+116
| | | | | | | | | | | | | | | | | Add IVO_T109NW41 serializable data to CBFS. Datasheet: T109NW41 R0 Tentative Product Specification.docx BUG=b:319025360 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Id740e3a21f72bbcd6e5c2b56b31ac90f4990d475 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79844 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* drivers/mipi: Add support for BOE_NV110WUM_L60 panelRuihai Zhou2024-01-083-0/+129
| | | | | | | | | | | | | | | | | Add BOE_NV110WUM_L60 serializable data to CBFS. Datasheet: B5NV110WUM-L60 V5.0Product SpecificationRev.P0 BUG=b:308968270 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78956 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* driver/wifi: DDR RFIM _DSM method function 3 report incorrect valueSimon Yang2024-01-041-1/+1
| | | | | | | | | | | | | | | | | The DDR RFIM _DSM method function 3 need to return: - 0: Enable DDR RFIM feature. - 1: Disable DDR RFIM feature. BUG=b:302084312 TEST=Build, dump SSDT to check _DSM function 3 return value Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
* drivers/intel/gma: Only show the choice when a VBT is to be addedArthur Heymans2023-12-261-0/+1
| | | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3bb71da8ea47f7365ae3895f5477f2a765256e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* drivers/intel/fsp2_0: Add boot mode stringsMarx Wang2023-12-261-1/+16
| | | | | | | | | | | | | | | | | | | | The FSP boot mode showing in serial log is a magic number. In order to let user understand its meaning directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [SPEW ] bootmode is set to: 2 with this change: [SPEW ] bootmode is set to: 2 (boot assuming no config change) Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* drivers/intel/fsp2_0: Log FW Splash Screen feature stateSubrata Banik2023-12-221-0/+3
| | | | | | | | | | | | | | | | | | | This patch implements debug logging to aid debugging and analysis of Firmware Splash Screen feature behavior. BUG=b:284799726 BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/screebo and check the FW splash screen state. [DEBUG] Firmware Splash Screen : Enabled Change-Id: I1ec7badf620e8dbe3d48674d93d640161de6a830 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* drivers/spi/gigadevice.c: Add GD25LQ255E supportTyler Wang2023-12-211-0/+7
| | | | | | | | | | | | | | | | datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf BUG=b:311336475 BRANCH=firmware-rex-15709.B TEST=Build AP-firmware and test on karis, system can boot to OS. Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79087 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* treewide: Use show_notices target for warningsMartin Roth2023-12-201-1/+1
| | | | | | | | | | | This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/spi: Add ISSI IS25WP256D flashMaximilian Brune2023-12-185-0/+41
| | | | | | | | | | | | | | datasheet: IS25WP256D Rev A13 (2023-08-03) tested: boot SiFive Hifive Unmatched board Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/uart/pl011.c Perform basic UART initNaresh Solanki2023-12-131-0/+32
| | | | | | | | | | | | | Configure UART baud rate, Line Control register as 8n1 with FIFO enable and enable UART TX and RX. Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth2023-12-1314-27/+27
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers: spi_flash: Add space before colon to fix coding styleTyler Wang2023-11-161-2/+2
| | | | | | | | | | | | BUG=none TEST=build karis firmware pass Change-Id: I67b4ca4c8fde795d4206eaa0b9ea9d9bfc768ac6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksumBill XIE2023-11-131-2/+5
| | | | | | | | | | | | | | | | | | | | | | | Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
* security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk2023-11-138-104/+74
| | | | | | | | | | | | | | | | | init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76954 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Allow to build romstage sources inside the bootblockArthur Heymans2023-11-092-3/+3
| | | | | | | | | | | | | | | | | | | | | | | Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers/i2c/lenovo_serials: Use buildtime constantsArthur Heymans2023-11-082-6/+3
| | | | | | | | | | | | The coreboot_version global variable just gets filled with the COREBOOT_VERSION macro so there is no reason to use a runtime strconcat. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3a2be7293d07ac591855ebd784bba350cdffa70f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78945 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* console/spkmodem: Make it work for bootblockArthur Heymans2023-11-071-0/+1
| | | | | | | | | | | | | This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4113dc3208fe15305d1132136dd33417dd086bfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/78935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/net/ne2k: Make it work for bootblockArthur Heymans2023-11-072-2/+2
| | | | | | | | | | | | | This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I708e8a3b503eb3a7fdf6063803d666529096f651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* Use common GCD functionYidi Lin2023-11-041-25/+8
| | | | | | | | | | Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella2023-11-022-29/+24
| | | | | | | | | | | Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/generic/adau7002: Set ACPI status to hiddenMatt DeVillier2023-11-011-1/+1
| | | | | | | | | | | | | | No driver available or needed under Windows, so hide from OS. TEST=build/boot Win11 on google/kahlee (liara), verify ADAU7002 device no longer listed as unknown under Device Manager. Boot Linux and verify audio still functional. Change-Id: If6d250a123825a69441b5c4d3cde35d5a68f568d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78510 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/gma/Kconfig: Add VBT compression configuration entryJeremy Compostella2023-10-262-1/+34
| | | | | | | | | | | | | | | | | | | | | | | Introduce Kconfig choice to pick between lzma, lz4 and no compression at all of the VBT binary. If VBT is needed in romstage, it can be used to set VBT lz4 compression as an alternative to enabling lzma compression support. Indeed, the extra lzma code needed to de-compress VBT undermines the compression size reduction between lzma and lz4. BUG=b:279173035 TEST=Verified that vbt.bin is lz4 compressed with VBT_CBFS_COMPRESSION_LZ4 and not compressed at all with VBT_CBFS_COMPRESSION_NONE Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* drivers/elog: Remove NULL check for array created in codeMartin Roth2023-10-251-4/+0
| | | | | | | | | | | | Checking to see if a the location of a static variable is NULL isn't super useful. If the check ever fails, there are much larger issues. Found-by: Coverity Scan #1452607 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6d3e012542287511f61807075c998efd6d10441e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78614 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEMArthur Heymans2023-10-251-1/+1
| | | | | | | | | | | The macro ENV_HAS_CBMEM achieves the same as this inline function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6d65ca51c863abe2106f794398ddd7d7d9ac4b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-28 03:43:17 +0000