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coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
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Coreboot firmware sources
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path:
root
/
src
/
include
/
device
/
dram
/
ddr2.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
include/device/dram: Add SPD lengths for DDR3 to DDR5
Martin Roth
2023-10-25
1
-3
/
+3
*
spd.h: Move enum ddr2_module_type to ddr2.h
Elyes Haouas
2023-01-04
1
-8
/
+5
*
src: Change bare 'unsigned' to 'unsigned int'
Martin Roth
2020-11-16
1
-15
/
+15
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
treewide: replace GPLv2 long form headers with SPDX header
Patrick Georgi
2020-05-06
1
-12
/
+1
*
treewide: Move "is part of the coreboot project" line in its own comment
Patrick Georgi
2020-05-06
1
-2
/
+1
*
src (minus soc and mainboard): Remove copyright notices
Patrick Georgi
2020-03-17
1
-1
/
+0
*
device/dram/ddr2.c: Add methods to compute to identify dram
Arthur Heymans
2018-04-09
1
-0
/
+1
*
device/ddr2,ddr3: Rename and move a few things
Arthur Heymans
2018-02-22
1
-58
/
+19
*
device/dram/ddr2.c: Store the checksum in the decoded SPD struct
Arthur Heymans
2017-12-20
1
-0
/
+1
*
device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag
Arthur Heymans
2017-09-22
1
-0
/
+2
*
device/dram/ddr2: Add a function to normalize tCLK
Arthur Heymans
2017-09-06
1
-1
/
+2
*
device/dram/ddr2.c: Fix is_registered_ddr2
Arthur Heymans
2017-06-09
1
-1
/
+1
*
device/dram/ddr2: Add common ddr2 spd decoder
Patrick Rudolph
2017-03-10
1
-0
/
+218