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* Clean up #ifsPatrick Georgi2012-05-087-8/+8
* Allow device ID arrays in the PCI driver structureVadim Bendebury2012-05-011-0/+1
* SMM: unify mainboard APM command handlersStefan Reinauer2012-04-271-1/+3
* cpu/cpu.h: add ROMCC guardsStefan Reinauer2012-04-271-2/+3
* Move top level pc80 directory to drivers/Stefan Reinauer2012-04-271-1/+1
* Revamp Intel microcode update codeStefan Reinauer2012-04-261-0/+21
* Replace cache control magic numbers with symbolsPatrick Georgi2012-04-251-0/+6
* S3 code in coreboot public folder.zbao2012-04-161-4/+6
* Add support for aligned allocationRon Minnich2012-04-121-0/+1
* Fixes and Sandybridge support for lapic cpu initStefan Reinauer2012-04-061-0/+3
* Add constants for fast path resume copyingStefan Reinauer2012-04-061-4/+13
* Fill out ChromeOS specific coreboot table extensionsStefan Reinauer2012-04-051-0/+36
* Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer2012-04-041-0/+2
* Add support for Intel Turbo Boost featureStefan Reinauer2012-04-031-0/+44
* smbios: add support for onboard devices extended informationStefan Reinauer2012-04-031-0/+29
* Add a helper function to determine the number of enabled CPUsStefan Reinauer2012-04-021-0/+1
* Align: Make sure 1 is treated as unsigned long instead of intStefan Reinauer2012-04-021-1/+1
* Make MTRR min hole alignment 64MBDuncan Laurie2012-03-301-0/+3
* Add more timestamps in coreboot.Stefan Reinauer2012-03-301-2/+20
* Add timestamps for selfboot and acpi wakeDuncan Laurie2012-03-301-0/+2
* Add TPM support to corebootStefan Reinauer2012-03-301-0/+29
* Add an option to keep the ROM cached after romstageStefan Reinauer2012-03-301-3/+4
* Add infrastructure for global data in the CAR phase of bootGabe Black2012-03-291-0/+31
* Detect whether the OXPCIE card is really present while in the ROM stage.Gabe Black2012-03-291-0/+5
* Add support for enabling PCIe Common Clock and ASPMDuncan Laurie2012-03-292-0/+14
* Refactor publishing CBMEM addresses through coreboot table.Vadim Bendebury2012-03-291-2/+4
* Add timestamp table pointer to the coreboot table.Vadim Bendebury2012-03-291-0/+8
* CBMEM CONSOLE: Add CBMEM type for console buffer.Vadim Bendebury2012-03-291-0/+1
* CBMEM CONSOLE: Add CBMEM console driver implementation.Vadim Bendebury2012-03-292-0/+29
* Increase CBMEM to accommodate larger console.Vadim Bendebury2012-03-291-0/+5
* Add cmos helper functions for reading/writing a dwordDuncan Laurie2012-03-281-0/+16
* Add timestamp collecting to coreboot.Vadim Bendebury2012-03-282-0/+47
* Initialize CBMEM early.Vadim Bendebury2012-03-281-1/+3
* Add RDC R8610 PCI IDs.Rudolf Marek2012-03-271-0/+4
* xchg is atomic with side-effectsPatrick Georgi2012-03-161-1/+1
* Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is availableGabe Black2012-03-141-0/+2
* Increase size of the coreboot table areaStefan Reinauer2012-03-091-2/+2
* Add helper function to find a Local APIC by ID in the device tree.Duncan Laurie2012-03-091-0/+1
* move console includes to central console/console.hStefan Reinauer2012-03-092-28/+20
* Add an implementation for the memchr library functionGabe Black2012-03-091-0/+1
* Unify Local APIC address definitionsPatrick Georgi2012-03-081-1/+2
* pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci idsKerry Sheh2012-02-161-0/+3
* AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh2012-02-161-0/+41
* AMD Geode cpus: apply un-written naming rulesKyösti Mälkki2012-02-131-1/+1
* Add OPROM mapping support to corebootStefan Reinauer2012-02-071-0/+1
* RD890: pci_ids updateKerry Sheh2012-01-241-3/+8
* post code: Replaced hard-coded post code with macroVikram Narayanan2012-01-231-0/+7
* lib: add ram_check_nodieSven Schnelle2012-01-121-0/+1
* MTRR: get physical address size from CPUIDSven Schnelle2012-01-101-1/+1
* Fix CMOS handling for non-USE_OPTION_TABLE configurationPatrick Georgi2011-12-131-2/+1
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