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* device/i2c_bus: Constify i2c_busdev and i2c_linkMatt DeVillier2022-04-011-2/+2
| | | | | | | | | Change-Id: If795087ecdaea24ad7834dcc6d5bf6a72f2aea8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/intel/dptf: Add support for Power participantVarshit B Pandya2022-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "INTC1060") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd/helpers: Remove redundancy with libpayload definesJakub Czapiga2022-03-301-6/+0
| | | | | | | | | | | | | Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h Remove redundant defines from libpayload.h and libpayloads' standard headers. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM valuesElyes Haouas2022-03-281-2/+2
| | | | | | | | | | | | Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09. There is no affected board in coreboot tree. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* include/espi.h: Switch to types.hRaul E Rangel2022-03-271-1/+1
| | | | | | | | | | | | | | We use bool in this file, so switch to using types.h. BUG=b:226635441 TEST=Build skyrim with DEBUG_ESPI Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I78b579de4e3832dd49a18413bf5d03870e347c91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63092 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/efi: Add EFI Status code definitionsSubrata Banik2022-03-251-0/+12
| | | | | | | | | | | | | | | | | This patch adds EFI status code macros in `efi_datatype.h` to implement FSP debug event handler natively in coreboot. Added `PiStatusCode.h` and `StatusCodeDataTypeId.h` files for `UDK base >= 2017`, as these files were added with UDK version 2017. BUG=b:225544587 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* include/efi: Add correct header file for EFI_PROCESSOR_INFORMATIONSubrata Banik2022-03-251-0/+1
| | | | | | | | | | | | | | | | This patch resolves compilation issue of including `efi_datatype.h` in other stage files due to unresolved EFI_PROCESSOR_INFORMATION macro definition. EFI_PROCESSOR_INFORMATION defined in `Protocol/MpService.h` hence, included to resolve compilation issue. TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd Reviewed-on: https://review.coreboot.org/c/coreboot/+/63010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/net/r8168: Add support for Realtek RTL8111KRaihow Shi2022-03-241-3/+4
| | | | | | | | | | | | | | The Realtek RT8168 and RTL8111K have a similar programming interface, therefore add the PCI device ID for the RTL8111K into driver for support. BUG=b:226253265 TEST=emerge-brask coreboot chromeos-bootimage. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* soc/intel/adl-n: Add device ID for TCSS XHCIMaulik V Vaghela2022-03-231-0/+1
| | | | | | | | | | | | | | | | | | | | This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* include/efi: Clean up efi_datatype.h fileSubrata Banik2022-03-171-6/+9
| | | | | | | | | | | | | | | | | | | | | | | This patch cleans up `efi_datatype.h` to allow other SoC and/or driver code to use this file. `PiPei.h` file only gets added from UDK2017 hence, the platform with the older EDK2 base (prior to UDK2017) is unable to resolve this file dependency. This CL removed the `PiPei.h` header and only added the required header file `PiPeiCis.h` for platforms with UDK base >= 2017. BUG=b:200113959 TEST=Able to build Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cpu/x86/smm: Add weak SoC init and exit methodsRaul E Rangel2022-03-101-0/+3
| | | | | | | | | | | | | | | | | | | | | This change provides hooks for the SoC so it can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* cpu/intel/common: Add support for energy performance preference (EPP)Cliff Huang2022-03-091-0/+3
| | | | | | | | | | | | | This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-092-1/+89
| | | | | | | | | | Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* prog_loader: Change legacy_romstage_select_and_load() to return cb_errJulius Werner2022-03-091-3/+2
| | | | | | | | | | | This is passing through a cb_err from cbfs_prog_stage_load(), so it should be declared to return that as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/62656 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMIRaul E Rangel2022-03-092-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This change will allow the SMI handler to write to the cbmem console buffer. Normally SMIs can only be debugged using some kind of serial port (UART). By storing the SMI logs into cbmem we can debug SMIs using `cbmem -1`. Now that these logs are available to the OS we could also verify there were no errors in the SMI handler. Since SMM can write to all of DRAM, we can't trust any pointers provided by cbmem after the OS has booted. For this reason we store the cbmem console pointer as part of the SMM runtime parameters. The cbmem console is implemented as a circular buffer so it will never write outside of this area. BUG=b:221231786 TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are visible when running `cbmem -1`. Perform a suspend/resume cycle and verify new SMI events are written to the cbmem console log. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* coreboot_tables.c: Expose the ACPI RSDPArthur Heymans2022-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | The ACPI RSDP can only be found in: - legacy BIOS region - via UEFI service On some systems like ARM that legacy BIOS region is not an option, so to avoid needing UEFI it makes sense to expose the RSDP via a coreboot table entry. This also adds the respective unit test. Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd: Remove cb_err_tJulius Werner2022-03-092-7/+7
| | | | | | | | | | | | | | | | | cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/mmio.h: Move readXp/writeXp helpers to device/mmio.hJianjun Wang2022-03-081-0/+40
| | | | | | | | | | | | These helpers are not architecture dependent and it might be used for different platform. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Make PCI ID define names shorterFelix Singer2022-03-071-4122/+4122
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/amd/sabrina: Add XHCI configurationJon Murphy2022-02-281-0/+1
| | | | | | | | | | | | | | Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/acpi/acpi.h: Drop non-existing acpi_create_madt_lapic_nmis()Elyes Haouas2022-02-221-2/+0
| | | | | | | | Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* [acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in commentsElyes Haouas2022-02-211-1/+1
| | | | | | | | | Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'Elyes HAOUAS2022-02-211-15/+0
| | | | | | | | | | 'printram(x, ...)' is already defined in 'include/device/dram/common.h' file Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/acpi: Add macro for FADT Minor Version and use itElyes Haouas2022-02-211-7/+17
| | | | | | | | Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
* arch/x86/acpi: Add code for KEY_MENUBoris Mittelberg2022-02-181-0/+1
| | | | | | | | | | | | | | | | Support of MENU key (aka hamburger) for Chromebooks with Vivaldi keyboard BUG=b:215038215 TEST=manually tested on Anahera device: pressing T13 key opens menu Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835 Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/acpi/acpi.h: Drop non-existing update_ssdt()Elyes Haouas2022-02-181-2/+0
| | | | | | | | Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* include/acpi/acpi.h: Drop non-existing update_ssdtx()Elyes Haouas2022-02-181-1/+0
| | | | | | | | Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* acpi: Use ACPI macros to configure USB port _PLD objectSubrata Banik2022-02-181-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds two ACPI macros for USB port A and C _PLD object configuration as: 1. ACPI_PLD_TYPE_A 2. ACPI_PLD_TYPE_C The configurable parameters are - Panel, Port is exposed on which face of a panel. - Horizontal, Horizontal position on the panel where the device connection point resides. - Group - Token, Unique numerical value identifying a group. - Position, Identifies this device connection point’s position in the group (i.e. 1st, 2nd). BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* device: Add support for PCIe Resizable BARsTim Wawrzynczak2022-02-162-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability. When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range. This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig. BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Correct Alder Lake M/N ESPI device IDKrishna Prasad Bhat2022-02-161-1/+1
| | | | | | | | | | | | | Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign it to the correct value. Reference documents: 619501, 645548. Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P2022-02-111-61/+61
| | | | | | | | | | | | | | | Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M IDs in the current code. Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N platform. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* src/arch/ppc64/*: pass FDT address to payloadSergii Dmytruk2022-02-111-0/+3
| | | | | | | | | | | | | It's available in %r3 in bootblock and needs to be passed to payload in %r27. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* src/cpu/power9: add file structure for power9, implement SCOM accessIgor Bagnucki2022-02-112-0/+231
| | | | | | | | | | Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* soc/intel/common: Add Crash Log and PMC SRAM PCI device IDsTim Wawrzynczak2022-02-101-4/+8
| | | | | | | | | | | | | Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device IDs. Document Number: 619501, 645548 Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* device: Add pciexp_find_next_extended_cap functionTim Wawrzynczak2022-02-101-0/+2
| | | | | | | | | | | | | | | | | | | Some PCIe devices have extended capability lists that contain multiples instances of the same capability. This patch provides a function similar to pciexp_find_extended_cap that can be used to search through multiple instances of the same capability by returning the offset of the next extended capability of the given type following the passed-in offset. The base functionality of searching for a given capability from an offset is extracted to a local helper function and both pciexp_find_extended_cap and pciexp_find_next_extended_cap use this helper. Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"Felix Held2022-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ceaf959678905f44a54a116f37bd15acab5d4608. The AMD Picasso SoC doesn't support x2APIC and neither advertises the presence of its support via bit 21 in EAX of CPUID leaf 1 nor has the bit 10 in the APIC base address MSR 0x1b set, but it does have 0xd CPUID leaves, so just checking for the presence of that CPUID leaf isn't sufficient to be sure that EDX of the CPUID leaf 0xb will contain a valid APIC ID. In the case of Picasso EDX of the CPUID leaf 0xb returns 0 for all cores which causes coreboot to get stuck somewhere at the end of MP init. I'm not 100% sure if we should additionally check bit 21 in EAX of CPUID function 1 is set instead of adding back the is_x2apic_mode check. TEST=Mandolin with a Picasso SoC boots again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1e3c55ce2d048b14c08e06bb79810179a87993d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* console: Add compile-time fast path when only CBMEM console is usedJulius Werner2022-02-071-0/+11
| | | | | | | | | | | | | | | | | A common use case when running coreboot on production systems is that only the CBMEM console (the one with the least impact on boot speed) is enabled. In this case, some of the code in the console subsystem has no effect. Due to the way it's all genericized over multiple consoles and tied together with function pointers, not all of this can be compile-time eliminated automatically, so this patch adds a little helper to facilitate that. This results in roughly 200 (compressed) bytes of savings per stage on an arm64 system. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1d5b8bda80d02a13ee0b7835e0805c4319fd21d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: Add loglevel prefix to interactive consolesJulius Werner2022-02-071-0/+5
| | | | | | | | | | | | | | | | | | | | | In an attempt to make loglevels more visible (and therefore useful, hopefully), this patch adds a prefix indicating the log level to every line sent to an "interactive" console (such as a UART). If the code contains a `printk(BIOS_DEBUG, "This is a debug message!\n"), it will now show up as [DEBUG] This is a debug message! on the UART output. "Stored" consoles (such as in CBMEM) will get a similar but more space-efficient feature in a later CL. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cpu/x86/mp_init.c: Rename num_concurrent_stacksArthur Heymans2022-02-071-2/+2
| | | | | | | | | | | This is just the amount of cpus so rename it for simplicity. Change-Id: Ib2156136894eeda4a29e8e694480abe06da62959 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/smm: Improve smm stack setupArthur Heymans2022-02-072-24/+8
| | | | | | | | | | | | Both the relocation handler and the permanent handler use the same stacks, so things can be simplified. Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki2022-02-051-1/+1
| | | | | | | | | | | | | | | | Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/lapic: Fix choice X2APIC_ONLYKyösti Mälkki2022-02-051-0/+8
| | | | | | | | | | | | | | When sending self an IPI, some instructions may be processed before IPI is serviced. Spend some time doing nothing, to avoid entering a printk() and acquiring console_lock and dead-locking. Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/lapic: Add lapic_send_ipi_self,others()Kyösti Mälkki2022-02-051-0/+11
| | | | | | | | | | | | This avoids unnecessary passing of APIC ID parameter and allows some minor optimisation for X2APIC mode. Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/lapic: Unify some parameterKyösti Mälkki2022-02-051-5/+5
| | | | | | | | Change-Id: I790fddea747f5db0536159e6c2ac90ea1da2830e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/lapic: Support switching to X2APIC modeKyösti Mälkki2022-02-052-1/+2
| | | | | | | | | | | | | | | | | | | | | The options X2APIC_ONLY and X2APIC_RUNTIME were already user-visible choices in menuconfig, but the functionality was not actually provided except for platforms where FSP presumably enabled X2APIC. Add the logic and related logging for switching to X2APIC operation. TEST: qemu-system-x86_64 -M Q35 -accel kvm -bios coreboot.rom -serial stdio -smp 2 PARALLEL_MP, and either X2APIC_ONLY or X2APIC_RUNTIME, need to be selected for the build of emulation/qemu-q35. Change-Id: I19a990ba287d21ccddaa64601923f1c4830e95e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if availableKyösti Mälkki2022-02-051-1/+1
| | | | | | | | | | | | | | Even when we're not in X2APIC mode, the information in CPUID leaf 0xb will be valid if that leaf is implemented on the CPU. Change-Id: I0f1f46fe5091ebeab6dfb4c7e151150cf495d0cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/smm: Retype variablesArthur Heymans2022-02-031-3/+3
| | | | | | | | Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* cpu/x86/smm: Add SMM_LEGACY_ASEGKyösti Mälkki2022-02-011-8/+0
| | | | | | | | | | | Followup will allow use of PARALLEL_MP with SMM_ASEG so some guards need to be adjusted. Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/alderlake: Add Alder Lake P IGD device IDsKane Chen2022-01-311-0/+3
| | | | | | | | | | | | | | This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Include Alder Lake-N device IDsUsha P2022-01-251-0/+12
| | | | | | | | | | | | Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 15:49:11 +0000