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* treewide: Move list.h to commonlibMaximilian Brune2024-02-243-31/+4
| | | | | | | | | | | It is needed in order to move device_tree.c into commonlib in a subsequent commit. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu2024-02-201-0/+4
| | | | | | | | | | | | | | Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes2024-02-191-0/+1
| | | | | | | | | | This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop unused soft_reserved_ram_resource macroFelix Held2024-02-141-3/+0
| | | | | | | | | | | | The unused soft_reserved_ram_resource expanded to the non-existent fixed_mem_resource function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* include/device/azalia_device.h: Add enum for misc fieldNicholas Chin2024-02-131-2/+7
| | | | | | | | | | | | | | | | The HDA specification defines bits 11:8 of the Configuration Default register as a miscellaneous field for other jack information. Only bit 8 has a standard meaning, and indicates that the jack does not have presence detect capability. Add an enum for use in the AZALIA_PIN_DESC macro to indicate this field. Note that many vendor firmwares set bits 11:9 to non zero values despite them being reserved in the specification, and their meaning in these cases is not well known. Change-Id: I70cbfca8541828a1e0c7280887060c04e4c71721 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* acpi/acpi: Pass struct device to acpi_create_srat_gia_pciPatrick Rudolph2024-02-091-1/+1
| | | | | | | | | | | | | | Instead of S:B:D:F numbers pass the struct device to acpi_create_srat_gia_pci and let it extract the information needed. This also adds support for PCI multi segment groups. Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80258 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi: Add MTCL function to ACPI SSDTDavid Ruth2024-02-062-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related to MTCL * Add write_mtcl_aml function to convert the byte data into the format expected by the MTCL functionality in the Linux kernel. * Add validate_mtcl function to validate that the byte data read in from a file is in the expected format. * Add write_mtcl_function function to read a binary file called "wifi_mtcl".bin" from cbfs, then call validate_mtcl to verify that it is in an expected format, and if so write the aml via acpigen * Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Add config flag CONFIG_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.bin" * Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for MTK WiFi devices when USE_MTCL is enabled. * Add MediaTek VID to src/include/device/pci_ids.h. BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.bin blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth@chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80170 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* lib: Move IP checksum to commonlibJulius Werner2024-02-021-8/+0
| | | | | | | | | | | | | | | | | | | | | | This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* cpu/x86/smm/pci_resource_store: Store DEV/VEN IDPatrick Rudolph2024-01-311-0/+2
| | | | | | | | | | | Allow SMM to verify the list of provided PCI devices by comparing the device and vendor ID for each PCI device. Change-Id: I7086fa450fcb117ef8767c199c30462c1ab1e1b6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/device.h: Rename busses for clarityArthur Heymans2024-01-312-11/+6
| | | | | | | | | | This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-311-2/+0
| | | | | | | | | | | | | | | | | | | | | | | Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* device/device.h: Drop multiple linksArthur Heymans2024-01-291-4/+3
| | | | | | | | | | | | | | | | | | | | Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* device: Add a helper function to add a downstream busArthur Heymans2024-01-291-3/+3
| | | | | | | | | | | | Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src, util: Update toolchain.inc references to .mkMartin Roth2024-01-261-1/+1
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ieaf7894f49a90f562b164924cc025e3eab5a3f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel: Add Lunar Lake device IDsAppukuttan V K2024-01-242-0/+73
| | | | | | | | | | | | | | | | Added Lunar Lake specific CPU and PCIE device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79899 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* device/device_util: Add method to retrieve the domainPatrick Rudolph2024-01-241-0/+1
| | | | | | | | | | | | | | Add a function to return the PCI domain device for the specified device. On multi PCI domain platforms this function allows to determine which domain and thus which socket the PCI device belongs to. Change-Id: I0068b82e139fe7a35e6b1b91b7d386b750c80748 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device: Add inline method to identify PATH_ROOTPatrick Rudolph2024-01-241-0/+9
| | | | | | | | | | | Add and use inline method to identify the root device. Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/device.h: Drop acpi_inject_dsdtArthur Heymans2024-01-221-1/+0
| | | | | | | | | | | | | This is now unused in the tree and filling SSDT should always be used. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* device_util: Drop unused function bus_pathArthur Heymans2024-01-211-1/+0
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id23a291af20473c3b3e67178b66fcde920d49984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* include/bootmem.h: Add commentMaximilian Brune2024-01-181-0/+1
| | | | | | | | Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I8f6752e887af8c1ceba56153e3da864abd040ffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79947 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/device.h: Fix outdated commentArthur Heymans2024-01-181-8/+1
| | | | | | | | | | | | | | LAPIC devices in devicetree is not possible any longer since commit 3eba665 "util/sconfig: Remove lapic devices from devicetree parsers". TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* device: Add support for multiple PCI segment groupsFelix Held2024-01-163-1/+16
| | | | | | | | | | | | | | | | | | Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new segment_group struct element and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* include/device/pci_mmio_cfg: assert CONFIG_ECAM_MMCONF_BUS_NUMBER != 0Felix Held2024-01-151-0/+4
| | | | | | | | | | | | | Make sure that CONFIG_ECAM_MMCONF_BUS_NUMBER is non-zero when the ECAM_MMCONF_SUPPORT Kconfig option is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic102b7dca9ffebb2d384a068a1fb1f4b6fb6c5f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79933 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* lib/smbios: rename segment group parameter of smbios_write_type41Felix Held2024-01-131-1/+1
| | | | | | | | | | | Rename the segment group parameter of smbios_write_type41 from 'segment' to 'segment_group' to be in line with the PCI specification. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79926 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/smbios: add segment_group parameter to smbios_write_type9Felix Held2024-01-131-1/+2
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* acpi/acpigen: add acpigen_write_SEG for segment group number methodFelix Held2024-01-131-0/+1
| | | | | | | | | | | Introduce acpigen_write_SEG to generate the ACPI method object that returns the PCI segment group number for a PCI(e) host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* vc/google: Show different logos for different ChromeOS devicesShelley Chen2024-01-111-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for showing different logos on the ChromeOS firmware splash screen based on the device model (between Chromebook-Plus and regular ChromeOS devices like Chromebook and Chromebox). This allows OEMs to customize the branding on their devices. This patch also introduces three new Kconfigs: - CHROMEOS_FW_SPLASH_SCREEN - CHROMEOS_LOGO_PATH - CHROMEBOOK_PLUS_LOGO_PATH which allow users to enable the fw splash screen feature in the vendorcode. Previously, we were using the BMP_LOGO Kconfig in drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be located inside the architecture specific files. BUG=b:317880956 BRANCH=None TEST=emerge-rex coreboot chromeos-bootimage verify that FW splash screen appears Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79775 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* cpu/x86/smi_trigger: use enum cb_err as apm_control return typeFelix Held2024-01-101-1/+1
| | | | | | | | | | | | | | Even though the return value from apm_control isn't checked at any of its call sites, using the cb_err enum instead of an integer as return type makes it clearer what the returned value means. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07ced74cae915df52a9d439835b84237d51fdd11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79835 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* sb/intel/bd82x6x: Add defines for PCI IDsPatrick Rudolph2023-12-231-0/+44
| | | | | | | | | | Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* x86: Separate CPU and SoC physical address sizeJeremy Compostella2023-12-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/spi: Add ISSI IS25WP256D flashMaximilian Brune2023-12-181-0/+1
| | | | | | | | | | | | | | datasheet: IS25WP256D Rev A13 (2023-08-03) tested: boot SiFive Hifive Unmatched board Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* acpi: Add support for WDAT tableMarek Maslanka2023-12-151-0/+94
| | | | | | | | | | | | | | | | | | | | | | This commit lays the groundwork for implementing the ACPI WDAT (Watchdog Action Table) table specification. The WDAT is a special ACPI table introduced by Microsoft that describes the watchdog for the OS. Platforms that need to implement the WDAT table must describe the hardware watchdog management operations as described in the specification. See “Links to ACPI-Related Documents” (http://uefi.org/acpi) under the heading “Watchdog Action Table”. BUG=b:314260167 TEST=Mock the acpi_soc_fill_wdat function for a specific platform/soc and enable ACPI_WDAT_WDT in the kconfig. Check if the build passes successfully. Change-Id: Ieb82d1f69b2b7fffacfd2928bc71f8ff10498074 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* rules.h: Clean up ENV_HAS_HEAP_SECTIONArthur Heymans2023-12-151-2/+2
| | | | | | | | | | | | Commit ea2c1d3 "cpu/x86/smm: Remove heap" removed the ability to use heap in SMM, but the ENV_HAS_HEAP_SECTION macro was not updated appropriately. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5ae4a63a7bd1b27ae3e9c757aa8557f329aad0f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth2023-12-1310-12/+12
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpi_gic: Add GIC ITS subtableNaresh Solanki2023-12-061-0/+1
| | | | | | | | | | | Add support for generating GIC subtable ITS (Interrupt Translator Service). Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* acpi: Add IO Remapping Table structuresNaresh Solanki2023-12-062-0/+114
| | | | | | | | | | | | | Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* acpi: Add PPTT supportDavid Milosevic2023-12-021-1/+108
| | | | | | | | | | | | | | | | | | | | | This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/amd: Add DBG2 ACPI tableZheng Bao2023-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtypeFelix Held2023-12-021-1/+2
| | | | | | | | | | | | | | | | | The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79219 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpigen.c: Add resource consumer functions for mmioArthur Heymans2023-11-231-0/+1
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id9e4adcd976e1f56ef7f502d9df16dbefce95c3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79217 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi: Optimize enum acpi_tables layoutNaresh Solanki2023-11-201-5/+32
| | | | | | | | | | | | | Arrange ACPI table enum in a vertical and alphabetized format. This change aims to reduce conflicts between patches. Change-Id: I192339df771d6a3ae67358fe46334fe2b216b974 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79099 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop HAVE_ACPI_TABLES guardsFelix Held2023-11-171-2/+1
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when HAVE_ACPI_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop GENERATE_SMBIOS_TABLES guardsFelix Held2023-11-171-2/+2
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when GENERATE_SMBIOS_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* src: Remove unnecessary semicolons from the end of macrosMartin Roth2023-11-101-1/+1
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia005915a05d02725f77b52ccd7acebefaf25d058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78964 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm: Fix get_save_state calculationEugene D. Myers2023-11-101-0/+9
| | | | | | | | | | | | | | | | | | | | When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100) of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. This patch addresses the issue identified in CB:76601, which means that SMMSTOREv2 now works with the STM. Thanks to Jeremy Compostella for suggesting this version of the patch. Resolves: https://ticket.coreboot.org/issues/511 Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Signed-off-by: Eugene D. Myers <edmyers@cyberpackventures.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Allow to build romstage sources inside the bootblockArthur Heymans2023-11-0910-25/+25
| | | | | | | | | | | | | | | | | | | | | | | Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* console.c: Enable gdb support in bootblockArthur Heymans2023-11-071-1/+1
| | | | | | | | | | | | | This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I34812fbcd1222eceeb9870b9cbb7431ead63ce6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78936 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console/spkmodem: Make it work for bootblockArthur Heymans2023-11-071-1/+1
| | | | | | | | | | | | | This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4113dc3208fe15305d1132136dd33417dd086bfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/78935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/net/ne2k: Make it work for bootblockArthur Heymans2023-11-071-1/+1
| | | | | | | | | | | | | This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I708e8a3b503eb3a7fdf6063803d666529096f651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* include/device/dram: Add SPD lengths for DDR3 to DDR5Martin Roth2023-10-254-3/+12
| | | | | | | | | | | | | | DDR2 already had a define to specify the SPD length, but other memory types did not. This led to the value being coded into other locations. Unify the definition for DDR2 to DDR5 and put the value at the top of the respective header file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id13b9c5d311984d4a98b831a8746d1659724aa96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 06:18:11 +0000