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* mb/google/bluey: Set correct Kconfig defaults for peripheralsHEADmainSubrata Banik9 hours2-4/+4
| | | | | | | | | | | | | | | | | | | | | Update the default Kconfig values for the google/bluey mainboard to specify the correct hardware instances/buses used for various peripherals as per bluey schematics (dated 04/15). Changes: - TPM I2C bus set to 0x10. - ChromeEC SPI bus set to 0xb. Removes previous TODO placeholders. BUG=b:404985109 TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC. Change-Id: I48283e9f5b9dc1d2f203dadbdf6d4e27566f0a83 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/qualcomm/x1p42100: Set correct Kconfig defaults for peripheralsSubrata Banik9 hours1-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Update the default Kconfig values for the `soc/qualcomm/x1p42100` to specify the correct hardware instances/buses used for various peripherals as per datasheet for bluey (dated 04/15). Changes: - Boot SPI flash bus set to 24. - Console UART instance set to 21. - Select FIXED_UART_FOR_CONSOLE Kconfig as UART is not really selectable due to GPIO Function 0 (bit-bang mode) default configuration. Additionally, remove previous used TODO placeholders. BUG=b:404985109 TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC. Change-Id: Ia053edb731f7e08c98ffa3fe273ddd1c97b651bb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87272 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/qualcomm/x1p42100: Add QUP Serial Engine (SE) entriesSubrata Banik9 hours6-29/+435
| | | | | | | | | | | | | | | | | | | | | | | This patch adds QUP-SE entries as applicable for the Qualcomm X1P-42-100 SoC. This includes: - Add new entries for QUPV3_2 SEs. - Update base addresses for all QUP-SEs. - Base GPIO pin function assignments. - Definition and GPIO mapping for relevant QUP Serial Engines (SEs). - GPIO mapping for the QSPI interface. Additionally, update GPIO PINS for QSPI and UART. BUG=b:404985109 TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC. Change-Id: Ib0535aa5dfadef8c412c5e9dd51859068539821f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/var/uldrenite: Configure GPP_A16 as NF4Kapil Porwal19 hours1-1/+1
| | | | | | | | | | | | | | | | GPP_A16 was wrongly configured to NF2 instead of NF4 i.e. ISH_GP5. Reference: Intel doc#648094 BUG=b:410645679 TEST=Check GPIO config in the OS. Change-Id: Ic91ac116513e27992679b0d301afed3bc057bf71 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87444 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yuval Peress <peress@google.com>
* sb/intel/lynxpoint: Add CFR objects for existing optionsMatt DeVillier22 hours1-0/+55
| | | | | | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them without duplication. TEST=build/boot google/panther with CFR options enabled. Change-Id: I5067e7a69f1f53f0f93d337198d3c349facec086 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/broadwell: Add CFR objects for existing optionsMatt DeVillier22 hours1-0/+38
| | | | | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them without duplication. TEST=build/boot google/guado with CFR options enabled. Change-Id: Iaf9950a3b446b1b55d836e54e8b231d047571768 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87387 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Increase EC status timeout to 30 secondsPranava Y N22 hours1-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some ITE ECs take long time (15-20s) to complete flash erase operation during EC software sync. Increasing the timeout value to 30s avoids EC_CMD_FLASH_ERASE command from timing out. As this is just a timeout value, it should not have any effect on the boot time. BUGS=b:386920751, b:412210635 TEST= Verify that the EC_CMD_FLASH_ERASE(0x13) is not timing out while performing EC sync. Below error is avoided, ``` [ERROR] Timeout waiting for EC process command 19! [INFO ] VB2:update_ec() vb2ex_ec_update_image(select) returned 0x10000001 [INFO ] VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1 [INFO ] VB2:sync_ec() update_ec(ctx, select_rw) returned 0x10000001 [INFO ] VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1 [INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x10000001 [INFO ] Saving nvdata [ERROR] EC software sync failed (0x10000001), rebooting [INFO ] board_reset() called! [INFO ] full_reset() called! ``` Change-Id: Id7bfa620e8c19d5b162b60e5cc37003ff339b589 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87427 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/cannonlake: Add CFR objects for existing optionsMatt DeVillier22 hours1-0/+87
| | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them without duplication. Change-Id: I925002958b5de93e833f06fddf772e5334a7bdb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* soc/intel/cannonlake: Hook up the VT-d setting to option APIMatt DeVillier22 hours1-1/+1
| | | | | | | | | | | | Hook up the VT-d setting to the option API, so it can be changed at runtime without recompilation. Change-Id: Iaddaf56563bd5916bc27d99171af48bf46127052 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87399 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* mb/google/nissa/var/pujjoniru: Support x32 memory configurationQinghong Zeng28 hours4-0/+27
| | | | | | | | | | | | | | | | | Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:409144310 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I7c1f48f89186c3803e8e6a1bf163b824f2f06731 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87250 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
* mb/google/brya: Create pujjocento variantKun Liu33 hours13-0/+1356
| | | | | | | | | | | | | | | | | | | | Create the pujjocento variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=b:409254508 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOCENTO Change-Id: I33b0642624ba67f53126e92976096ba53750ae89 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87419 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/bluey: Add initial support for BlueySubrata Banik35 hours13-0/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces basic support for the google/bluey mainboard, based on the Qualcomm X1P-42-100 SoC. Changes: - Add placeholder mainboard callbacks to enable control flow from /lib and Qualcomm SoC code. - Populate the bluey mainboard directory with a copy of the herobrine codebase, removing SoC/mainboard-specific implementations. This provides a minimal working build for google/bluey, allowing upstream builders to compile the mainboard. This facilitates easier verification of subsequent changes. BUG=b:404985109 TEST=Successfully built google/bluey with Qualcomm X1P-42-100 SoC. Change-Id: Id0da1846b8aef6f4ef4345be9cd803aa60406cdf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86973 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/qualcomm/x1p42100: Add initial SoC skeleton for X1P-42-100Subrata Banik35 hours22-0/+614
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a basic SoC framework for the Qualcomm X1P-42-100, enabling initial build integration. Key changes: - Add placeholder SoC callbacks to facilitate control flow from /lib and Qualcomm common code. - Populate the x1p42100 SoC directory with a copy of the SC7280 codebase, with SoC-specific implementations removed. This provides a foundational structure for X1P-42-100 development within the `soc/qualcomm/x1p42100` directory, ensuring the upstream builder can successfully compile the SoC code. This allows for incremental development and integration. Reference Document: X1P42100 Hardware Register Description BUG=b:404985109 TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC. Change-Id: I6358177b9c6dc26967d364a2056a62d8ca77f89b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFONaresh Solanki41 hours1-0/+1
| | | | | | | | | | | Use soc_fill_cpu_cache_info implementation to for computing L3 cache size accurately for Glinda SoC. Change-Id: I2827508ec0ae5f16d609e1bc76c00eb376a7b71b Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87222 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/cpu/noncar: Add SMBIOS helperNaresh Solanki46 hours1-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoC like Glinda, 1. It has multiple L3 caches block, each identified by a unique cache UID. Each core is associated with a specific L3 cache, which can be determined based on the CPU core ID. 2. Each CPU core have slightly different CPU boost frequency. For L3 cache info in DMI table type 7, the default implementation (x86_get_cpu_cache_info) retrieves cache information only for the current core and assumes that the same L3 cache is shared across all cores. To accurately determine the total L3 cache size: 1. Retrieves L3 cache information for each CPU core. 2. Identifies the unique cache ID associated with each core. 3. Aggregates cache sizes for all unique cache IDs to compute the total L3 cache size, ensuring correct summation even when L3 cache blocks have different sizes. Additionally to get core max boost frequency, 1. Determine max boost frequency among all cores & update smbios_cpu_get_max_speed_mhz such that it return max of all cores. TEST=Build for Glinda SoC & check output of `dmidecode -t 7` & `dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB (16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum boost clock frequency. Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* mb/google/fatcat/var/felino: Add Write Protect GPIO to cros_gpiosTongtong Pan47 hours1-0/+1
| | | | | | | | | | | | | | | | This enables the utility crossystem to access WP GPIO, `GPIO_PCH_WP` aka GPP_C08 is part of PTL GPIO community 0 therefore add `CROS_GPIO_DEVICE0_NAME` into the `cros_gpios` lists. BUG=b:409472563 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: Ia21b95d220d8df30fb3aa73b4c71047b135a52e6 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87426 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/mediatek/mt8189: Add I2C driver supportot_ryanw.wang2 days4-0/+214
| | | | | | | | | | | | | | | Add I2C controller driver. BUG=b:379008996 BRANCH=none TEST=build passed Signed-off-by: ot_ryanw.wang <ot_ryanw.wang@mediatek.com> Change-Id: I4baa291a83ecce60eb2d41e329c2182f3ea273b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/mediatek/common: Move I2C functions to common codeVince Liu2 days26-123/+55
| | | | | | | | | | | | | | | | | | To promote code reuse and maintainability, move i2c functions to common folder. The function prototype "mtk_i2c_bus_init(uint8_t bus)" used by some legacy platforms are changed to "mtk_i2c_bus_init(uint8_t bus, uint32_t speed)" for better API integration. BUG=b:379008996 BRANCH=none TEST=build passed. Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> Change-Id: I6ac7009f5af4e6379d3f73aec61d0f4abd28471c Reviewed-on: https://review.coreboot.org/c/coreboot/+/87352 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/ocelot: Select Wildcat Lake(WCL) SoC configSowmya Aralguppe2 days1-1/+1
| | | | | | | | | | TEST=Compiled and Verified on Wildcat Lake Simulation Platform. Change-Id: I0eed357931dfdc74509e6ed8c536fecba5a019f9 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/amd/crater: Fix some ec definesAna Carolina Cabral3 days1-18/+17
| | | | | | | | | | Fix some ec bits name and indentation. Change-Id: I23407e4e7be661980c16ef96dd0efabb3898e3da Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87304 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/crater: Add touchscreen supportAna Carolina Cabral3 days3-1/+34
| | | | | | | | | | Add edp I2C touch panel suport. Change-Id: I33f13fc4c76dfe7cb9abf114d31e83e7ad24bdb9 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/amd/crater: Add missing dxio descriptorsAna Carolina Cabral3 days2-1/+108
| | | | | | | | | | | Add DT, WLAN, WWLAN, TB and XGBE port descriptors according to PI source package #67683 (NDA). Change-Id: Iccc74fd03f6833112b370ba503d9d33033609c5b Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* smmrelocate: Drop unused parameterPatrick Rudolph3 days3-12/+12
| | | | | | | | | | | The parameter CPU isn't used, thus drop it. Change-Id: Ie7f6179f0545f905463752e94243b438143d8234 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* mb/starlabs/*: Unify Sleep S3 and S4 GPIO configurationsSean Rhodes3 days5-10/+10
| | | | | | | | | | Ensure all boards configure these two GPIOs to NF1. Change-Id: Ie8a222bff349a427083adb1c4d7ca73a41de3095 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/intel: Add Wildcat Lake CPU and PCIe device IDsAppukuttan V K3 days27-0/+193
| | | | | | | | | | | | | | | | | This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the header files and driver-specific code. Reference: Wildcat Lake Processor Prelim External Device IDs (820363) BUG=b:394208231 TEST=Verified on Wildcat Lake Simulation Platform Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/fatcat: Disable VR settings on Panther Lake H SoCJeremy Compostella3 days1-0/+47
| | | | | | | | | | | | | | | | | | | | | | | Introduce a new static function `disable_vr_settings_on_pantherlake_h()` to disable Voltage Regulator (VR) settings when a Panther Lake H System on Chip (SoC) is detected. The existing VR configurations, introduced by commit d19dd192dbe3 ("mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings"), are optimized for Panther Lake U SoC, which can cause performance issues on Panther Lake H boards under stress due to the I_TRIP value being lower than what the device could actually use. By disabling these settings, the Firmware Support Package (FSP) falls back to default values for the SoC, which are more suitable. TEST=Observe the "Disabling VR settings on PTL-H" log during a boot test on a Panther Lake H variant. Change-Id: Ifc371212259fa724425158ad9ebadebd30c81705 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/ocelot/var/ocelot: update gpiosNick Vaccaro3 days1-301/+298
| | | | | | | | | | | | | | Update gpio configuration to match ocelot schematic. BUG=b:412736286 BRANCH=None TEST=`emerge-ocelot coreboot` and verify it compiles without error. Change-Id: Id2e2eb9fdf008445124e99393fe4b192ccb27f5d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com>
* mb/google/ocelot: update FW_CONFIGNick Vaccaro3 days3-436/+37
| | | | | | | | | | | | | | | | | | | | | | Update the FW_CONFIG to correspond to the Google Ocelot hardware SKUs and remove code that is no longer needed due to the FW_CONFIG changes. Removed support for AUDIO_ALC722_SNDW, AUDIO_MAX98360_ALC56821_I2S, AUDIO_MAX98373_ALC5682_SNDW, TOUCHSCREEN_LPSS_I2C, UFC_MIPI, UFC_USB, WFC_MIPI and WFC_USB. Added support for AUDIO_ALC721_SNDW, DISPLAY_TOUCH_PRESENT, and DISPLAY_NO_TOUCH_PRESENT. BUG=b:412736286 BRANCH=None TEST=`emerge-ocelot coreboot` and verify it compiles without error. Change-Id: I5fd7010230a3f17005f5ca395ffaca0724a615e9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Add CFR objects for existing optionsMatt DeVillier3 days1-0/+106
| | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them without duplication. Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/cannonlake: Hook up S0ix setting to option APIMatt DeVillier3 days1-3/+4
| | | | | | | | | | | | Hook up the s0ix_enable setting to the option API, so it can be changed at runtime without recompilation. Default to the value set by the mainboard. Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* soc/intel/cannonlake: Hook up IGD config to option APIMatt DeVillier3 days1-1/+2
| | | | | | | | | | | | | | Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the option API, so they can be configured at runtime without recompilation. The Aperture size falls back to the FSP default value, so no change if unconfigured. Change-Id: Idad22ca79c10d575320b4360ec24c2019a837446 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* soc/intel/broadwell: Allow ME enable/disable to be set via optionMatt DeVillier3 days1-2/+3
| | | | | | | | | | | Add an option variable 'me_disable' to control the visibility of the HECI PCI device at runtime. Default to the Kconfig selection if not set. Change-Id: I6e7c018115780c74f1662948ed8dad3e0559051a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/lynxpoint: Allow ME enable/disable via optionMatt DeVillier3 days1-2/+3
| | | | | | | | | | | | Add an option variable 'me_disable' to control the visibility of the HECI PCI device at runtime. Default to the Kconfig selection if not set. Change-Id: I12c4c9f062cb5904c2f9c05b333bf0ed81aba632 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87384 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/samsung/stumpy: Clean up makefileMatt DeVillier3 days1-5/+5
| | | | | | | | | | | | | Organize according to stage, alphabetize, and guard inclusion of ChromeOS-specific code. TEST=build/boot stumpy Change-Id: Id6ea4e685ff3e098f6c619e1cab48a5a9320c29b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/samsung/stumpy: Use CFR setup menu to manage optionsMatt DeVillier3 days3-0/+40
| | | | | | | | | | | | | Enable support for managing system options via CFR, and select it by default when using edk2 with SMMSTORE. TEST=build/boot stumpy w/edk2 payload Change-Id: I91166a3932931c04eae78065fec6b856aebc6f0b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/option/cfr: Select EFI variable store when edk2 payload usedMatt DeVillier3 days1-0/+1
| | | | | | | | | | | | | | | | | Since CFR options require a backend to store the keys/values, select DRIVERS_EFI_VARIABLE_STORE when edk2 is used as the payload and SMMSTORE is enabled, so that boards only need to select DRIVERS_OPTION_CFR in order to have a fully-functioning configuration setup. TEST=build samsung/stumpy with DRIVERS_OPTION_CFR selected and edk2 payload used. Change-Id: Ib8565e4fefb1b3f05e58ab039be8ab0d1bc046f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/efi/fw_info: Select necessary UDK binding as neededMatt DeVillier3 days1-1/+1
| | | | | | | | | | | | | | DRIVERS_EFI_FW_INFO requires some Intel vendorcode headers which are selected by default on FSP 2.x platforms, but not by earlier ones. Select the oldest UDK binding for non-FSP 2.x boards, so that the required headers are available, rather than depending on UDK_BASE and requiring those boards to manually select the binding Change-Id: I27ab64ab0c9d4d45cc09061f6f8c3725c24df706 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/efi/variable_store: Select necessary UDK binding as neededMatt DeVillier3 days1-1/+1
| | | | | | | | | | | | | | | | | DRIVERS_EFI_VARIABLE_STORE requires some Intel vendorcode headers which are selected by default on FSP 2.x platforms, but not by earlier ones. Select the oldest UDK binding for non-FSP 2.x boards, so that the required headers are available, rather than depending on UDK_BASE and requiring those boards to manually select the binding. TEST=build samsung/stumpy with EFI variable store support, without manually selecting UDK_2017_BINDING at the mainboard level. Change-Id: I099d3cc7690a0faecfe32a8bc814766c67c63fbb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Add CFR objects for existing optionsMatt DeVillier3 days1-0/+83
| | | | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them without duplication. TEST=build/boot samsung/stumpy with CFR options enabled. Change-Id: Ia6906992deb948869ecfd8a5f6fc3883220811ec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* nb/intel/sandybridge: Add CFR objects for existing optionsMatt DeVillier3 days1-0/+34
| | | | | | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them. Currently only one option for IGD UMA size, but others can be added as needed. Change-Id: I892ffcc74d36a266697cbc7ea3c8880db6b67f44 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/intel/skylake: Add CFR objects for existing optionsMatt DeVillier3 days1-0/+87
| | | | | | | | | | | Add a header with CFR objects for existing configuration options, so that supported boards can make use of them without duplication. Change-Id: Id69295ae1708164b1afbafe5724e19bf13fc3963 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87393 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Hook up IGD config to option APIMatt DeVillier3 days1-1/+2
| | | | | | | | | | | | | | Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the option API, so they can be configured at runtime without recompilation. The Aperture size falls back to the FSP default value, so no change if unconfigured. Change-Id: Ic900cb7bdc6dc532aef0c0b51b32bf8308a8ae36 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87392 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Hook up S0ix setting to option APIMatt DeVillier3 days1-0/+1
| | | | | | | | | | | | Hook up the s0ix_enable setting to the option API, so it can be changed at runtime without recompilation. Default to the value set by the mainboard. Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* mb/starlabs/*: Select DRIVERS_OPTION_CFR_ENABLEDMatt DeVillier3 days5-5/+5
| | | | | | | | | | | | Per the documentation, mainboards should select `DRIVERS_OPTION_CFR_ENABLED` vs `DRIVERS_OPTION_CFR`, since the latter is meant to be user selectable. Change-Id: Ica2980fb9a8c69cae48e235ebbd72e824c24e010 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* superio/ite/it8772f: Program power state after failureMatt DeVillier3 days1-0/+1
| | | | | | | | | | | | | | | | | Allow the power state after failure to be set using an option backend if used, otherwise fall back to the Kconfig selection. This is a noop for all it8772f boards unless they enable an option backend, in which case that option setting is now functional, whereas before it would have been ignored for the Kconfig selection. TEST=build/boot google/panther with various power state after fail Kconfig selections. Change-Id: I1988d70fe27a287cd2cc91dbb905c243c24c816d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87383 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* superio/ite/*: Move setting of power state to common codeMatt DeVillier3 days5-64/+41
| | | | | | | | | | | | | | Move the programming of the power state after power failure to the ITE EC common code, in order to unify and extend to other ITE SIO chips. The implementations in the it8720f and it8728f are functionally identical, so take the "best" style elements of both, using clear variable names and defines for registers rather than magic values. Change-Id: I4b7e9455e964320f35997fdf04a515b942e030c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* soc/intel/cannonlake: Drop redundant PcieRpEnableNico Huber3 days53-381/+73
| | | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* soc/intel/skylake: Drop redundant PcieRpEnableNico Huber3 days45-208/+60
| | | | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Create epic variantYunlong Jia3 days12-0/+813
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create the epic variant of the nissa reference board by copying the template files to a new directory named for the variant. This variant is a Nirul project,support TWL devices and select BOARD_GOOGLE_BASEBOARD_NISSA. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) H9JCNNNCP3MLYR-N6E 3 (0011) BUG=404301972 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_EPIC Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87041 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/skywalker: Create variant ObiwanCong Yang3 days2-1/+6
| | | | | | | | | | | | | | | Create the variant Obiwan. BUG=b:406115783 TEST=emerge-skywalker coreboot BRANCH=None Change-Id: Ic3478653cee2906117b69aa7335864a0c7b95b29 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87397 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-26 12:30:12 +0000