| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 2 | -2/+0 |
| * | src/mainboard: Replace GPLv2 long form headers with SPDX header | Elyes HAOUAS | 2020-05-10 | 1 | -13/+1 |
| * | mainboard/asrock: Use SPDX for GPL-2.0-only files | Angel Pons | 2020-04-04 | 1 | -13/+2 |
| * | mainboard/[a-f]*: Remove copyright notices | Patrick Georgi | 2020-03-18 | 2 | -2/+0 |
| * | sb/intel/i82801gx: Add common LPC decode code | Arthur Heymans | 2019-11-12 | 1 | -0/+2 |
| * | sb/intel/i82801gx: Detect if the southbridge supports AHCI | Arthur Heymans | 2019-06-06 | 1 | -1/+0 |
| * | mb/*/devicetree.cb: Remove unavailable PCIe ports | Arthur Heymans | 2019-06-05 | 1 | -2/+0 |
| * | mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 | Arthur Heymans | 2018-11-12 | 1 | -3/+0 |
| * | mb/asrock/g41c-gs: Link separate gpio.c files | Arthur Heymans | 2018-09-18 | 1 | -0/+115 |
| * | mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree | Arthur Heymans | 2018-09-15 | 1 | -0/+4 |
| * | mb/asrock/g41c-gs: Add the revision 1 variant | Arthur Heymans | 2018-07-22 | 1 | -0/+155 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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