coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	mb///devicetree.cb: Normalize disabled PIRQ values	Angel Pons	2020-07-26	1	-6/+6
*	mainboard///*.cb: Remove leading blank lines from SPDX header	Elyes HAOUAS	2020-05-18	1	-3/+0
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi	2020-05-09	1	-9/+1
*	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi	2020-03-18	1	-2/+0
*	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans	2019-11-12	1	-0/+3
*	mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`4.10	Nico Huber	2019-07-20	1	-1/+0
*	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans	2019-06-06	1	-1/+0
*	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans	2019-06-05	1	-2/+0
*	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans	2018-11-12	1	-4/+6
*	mb/asus/p5gc-mx: Implement resume from S3 support	Arthur Heymans	2017-07-12	1	-1/+12
*	mb/asus/p5gc-mx: Fix and complete SIO devicetree options	Arthur Heymans	2016-12-28	1	-23/+37
*	mb/asus/p5gc-mx: Add mainboard	Arthur Heymans	2016-12-22	1	-0/+124