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coreboot.git
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4.1
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4.11_branch
4.12_branch
4.14_branch
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4.2
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4.22_branch
4.3
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path:
root
/
src
/
mainboard
/
emulation
/
spike-riscv
/
memlayout.ld
Commit message (
Expand
)
Author
Age
Files
Lines
*
memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
Patrick Georgi
2023-10-11
1
-1
/
+1
*
cbfs: Enable CBFS mcache on most chipsets
Julius Werner
2020-12-02
1
-1
/
+2
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
mainboard/emulation: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-04
1
-13
/
+2
*
mainboard/[a-f]*: Remove copyright notices
Patrick Georgi
2020-03-18
1
-1
/
+0
*
fmap: Make FMAP_CACHE mandatory if it is configured in
Julius Werner
2019-12-11
1
-1
/
+2
*
RISC-V boards: Remove PAGETABLES section from memlayout.ld
Jonathan Neuschäfer
2018-04-27
1
-1
/
+1
*
RISCV: Clean up the common architectural code
Ronald G. Minnich
2016-10-24
1
-1
/
+2
*
riscv-spike: Move coreboot to 0x80000000 (2GiB)
Jonathan Neuschäfer
2016-06-21
1
-6
/
+8
*
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-31
1
-4
/
+0
*
riscv-memlayout: fix existing memlayout issues, add sbi interface
Thaminda Edirisooriya
2015-09-16
1
-5
/
+5
*
riscv-spike: support for Spike emulation of riscv
Thaminda Edirisooriya
2015-08-09
1
-0
/
+32