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coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
classic-2014.10
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Coreboot firmware sources
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path:
root
/
src
/
mainboard
/
emulation
/
spike-riscv
/
uart.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
src/mainboard: Remove unnecessary space after casts
Elyes Haouas
2023-01-30
1
-1
/
+1
*
include/console/uart: make index parameter unsigned
Felix Held
2020-09-12
1
-1
/
+1
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
mainboard/emulation: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-04
1
-13
/
+2
*
mainboard/[a-f]*: Remove copyright notices
Patrick Georgi
2020-03-18
1
-1
/
+0
*
src: Use 'include <boot/coreboot_tables.h>' when appropriate
Elyes HAOUAS
2019-10-27
1
-1
/
+0
*
arch/io.h: Drop unnecessary include
Kyösti Mälkki
2019-03-04
1
-1
/
+0
*
mb/emulation/spike-riscv: Update UART address
Jonathan Neuschäfer
2017-06-12
1
-1
/
+1
*
riscv: Unify SBI call implementations under arch/riscv/
Jonathan Neuschäfer
2016-11-07
1
-1
/
+0
*
riscv-spike: Replace custom UART with a memory-mapped 8250
Jonathan Neuschäfer
2016-06-12
1
-33
/
+1
*
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-31
1
-4
/
+0
*
riscv-spike: support for Spike emulation of riscv
Thaminda Edirisooriya
2015-08-09
1
-0
/
+61