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* src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS2020-05-102-26/+2
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-095-45/+5
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-064-47/+4
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-064-8/+4
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-024-4/+4
* mainboard/foxconn: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-0414-183/+28
* mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons2020-03-202-24/+2
* mainboard/[a-f]*: Remove copyright noticesPatrick Georgi2020-03-1825-46/+0
* mb/*/Kconfig: Factor out MAINBOARD_VENDORAngel Pons2020-03-031-1/+1
* mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includesElyes HAOUAS2020-01-131-1/+0
* mb/foxconn/d41s/devicetree.cb: Indent with tabsAngel Pons2020-01-101-90/+89
* mb/*/*/acpi_tables: Remove unused includesElyes HAOUAS2020-01-022-2/+0
* mb/*/*/acpi_tables: Don't zero out gnvs againPeter Lemenkov2019-12-311-2/+0
* mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons2019-12-312-2/+0
* mb/*/*/early_init.c: Remove unused <device/pci_{def,ops}.h>Elyes HAOUAS2019-12-191-1/+0
* arch/x86: Make X86 stages select ARCH_X86Arthur Heymans2019-12-161-1/+0
* Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi2019-11-231-1/+1
* nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-152-1/+5
* nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans2019-11-151-42/+7
* mb/*/*(ich7/x4x): Use common early southbridge initArthur Heymans2019-11-141-13/+1
* sb/intel/i82801gx: Add common LPC decode codeArthur Heymans2019-11-124-22/+5
* mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'Elyes HAOUAS2019-11-111-1/+0
* mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.aslArthur Heymans2019-11-044-58/+2
* mb/intel/{i82801gx,x4x}: Don't select ASPM optionsArthur Heymans2019-11-031-3/+0
* soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik2019-11-012-2/+2
* sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans2019-10-111-1/+2
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-1/+1
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-3/+1
* sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans2019-06-062-2/+0
* mb/*/devicetree.cb: Remove unavailable PCIe portsArthur Heymans2019-06-051-2/+0
* nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-05-252-1/+4
* src: Add missing include 'console.h'Elyes HAOUAS2019-04-231-0/+1
* src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_configArthur Heymans2019-04-231-2/+1
* sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph2019-04-131-0/+1
* mb/foxconn/g41m: Fix overridetreeKyösti Mälkki2019-03-181-6/+8
* src/mainboard/*/*/cstates.c: Drop unused includesElyes HAOUAS2019-03-132-2/+0
* {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS2019-03-131-2/+0
* src/mb: Shorten 'include <arch/x86/include/arch/acpigen.h>'Elyes HAOUAS2019-03-081-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-083-4/+4
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-012-0/+2
* src: Remove unused include device/pnp_def.hElyes HAOUAS2019-02-071-1/+0
* nb/intel/pineview: Use parallel MP initArthur Heymans2019-01-231-1/+0
* nb/intel/x4x: Use parallel MP initArthur Heymans2019-01-231-1/+0
* nb/intel/pineview: Move the boilerplate mainboard_romstage_entryArthur Heymans2019-01-141-96/+5
* mb/foxconn/g41s-k: Add g41m variantArthur Heymans2019-01-1015-5/+150
* mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS2019-01-101-7/+0
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-092-6/+0
* sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans2019-01-082-6/+1
* mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6Arthur Heymans2019-01-081-1/+0
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