coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	util/sconfig: Remove unused ioapic and irq keywords	Arthur Heymans	2023-04-11	1	-30/+9
*	sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int'	Elyes Haouas	2023-04-08	1	-1/+1
*	mb/*: Remove lapic from devicetree	Arthur Heymans	2023-01-30	1	-5/+1
*	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	Arthur Heymans	2022-12-05	1	-3/+0
*	sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}	Elyes Haouas	2022-12-02	1	-2/+2
*	nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree	Arthur Heymans	2022-12-01	1	-0/+2
*	mb///devicetree.cb: Normalize disabled PIRQ values	Angel Pons	2020-07-26	1	-5/+5
*	mainboard///*.cb: Remove leading blank lines from SPDX header	Elyes HAOUAS	2020-05-18	1	-3/+0
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi	2020-05-09	1	-9/+1
*	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi	2020-03-18	1	-2/+0
*	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans	2019-11-12	1	-0/+3
*	mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`4.10	Nico Huber	2019-07-20	1	-1/+0
*	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans	2019-06-06	1	-1/+0
*	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans	2018-11-12	1	-4/+6
*	superio/ite/common: Add temperature offset	Vagiz Trakhanov	2017-10-22	1	-3/+4
*	nb/intel/i945: Make pci_mmio_size a devicetree parameter	Arthur Heymans	2016-12-11	1	-0/+2
*	mb/gigabyte/ga-945gcm-s2l: Configure SuperIO EC	Arthur Heymans	2016-11-28	1	-0/+25
*	mb/gigabyte/ga-945gcm-s2l: add mainboard	Arthur Heymans	2016-11-08	1	-0/+160