| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | sb/intel: Use `bool` for PCIe coalescing option | Angel Pons | 2022-01-04 | 1 | -1/+1 |
| * | cpu/intel/haswell: Factor out ACPI C-state values | Angel Pons | 2021-01-15 | 1 | -8/+0 |
| * | sb/intel/lynxpoint/sata: Always use AHCI mode | Angel Pons | 2020-11-10 | 1 | -2/+0 |
| * | lynxpoint: Factor out PIRQ routing from devicetree | Angel Pons | 2020-07-28 | 1 | -9/+0 |
| * | mb/*/*/devicetree.cb: Normalize disabled PIRQ values | Angel Pons | 2020-07-26 | 1 | -4/+4 |
| * | haswell: Move some MRC settings to devicetree | Angel Pons | 2020-07-12 | 1 | -0/+4 |
| * | mb/google/{beltino,jecht}: Drop SIO configuration lines | Nico Huber | 2020-01-07 | 1 | -4/+0 |
| * | mb/google,samsung/*: Add LPC TPM chip driver to devicetree | Matt DeVillier | 2018-08-01 | 1 | -0/+3 |
| * | Add Haswell Chromeboxes/Chromebase using variant board scheme | Matt DeVillier | 2016-11-24 | 1 | -0/+140 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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