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* mb/google/brya/acpi: Fix PERST# handling in GC6 exitTim Wawrzynczak2022-08-071-1/+1
| | | | | | | | | | | | | | | PERST# is supposed to be de-asserted in GC6 exit, but the original patch used the CTXS Method, which drives a GPIO low, instead of STXS, because PERST# is active-low. This patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Fix NVJT subfunction IDsTim Wawrzynczak2022-08-071-2/+2
| | | | | | | | | | | | | | | | The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed these are supposed to be 3 and 4, also respectively, so this patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak2022-07-281-2/+0
| | | | | | | | | | | | | | | | | | | | | After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/acpi: Poll more frequently in GPPLTim Wawrzynczak2022-07-221-2/+3
| | | | | | | | | | | | | | | | | | | The full dGPU power-on sequence, when executed from ACPI, is taking roughly 15ms or so, which puts it close to the maximum of 20ms required from the Nvidia spec. Changing the polling period to 100 us instead of 1 ms drastically reduces the time required for this sequence, now taking typically 7 ms or so. This gives a lot more margin during the power on sequence. BUG=b:238466724 TEST=Sequence verified by EE on a scope Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Add support for D Notify event from the Chrome ECTim Wawrzynczak2022-07-203-0/+52
| | | | | | | | | | | | | | | | | | | | | The agah EC code includes a driver to keep track of the current D Notify level that the GPU should be at. When it changes, it will send a host event to the ACPI FW, which will then pass that Notify on to the kernel driver. This patch adds support for that feature, which is described in the Nvidia Software Design Guide. BUG=b:229405562 TEST=add Printf() calls to the ACPI, and work through the various scenarios on the EC that will cause D Notify levels to change; this will cause the Printfs() to show up in the kernel log. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Fix GPIO assignment for GPIO_GPU_NVVDD_ENTim Wawrzynczak2022-07-131-1/+1
| | | | | | | | | | | | GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in power.asl, but a double check of the schematic shows that the actual pad is GPP_A17, so this patch fixes that. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Remove NV_33 power rail from GC6 entry/exit sequencesTim Wawrzynczak2022-07-131-12/+0
| | | | | | | | | | | | | | | | | I misread my notes when writing the code for the GC6I/GC6O Methods, and accidentally included NV_33 in the GC6 sequence, which is incorrect (confirmed in the Hardware Design Guide). This patch removes the code that brings NV_33 up and down during the GC6 sequences. BUG=b:236676400 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565 Reviewed-by: Robert Zieba <robertzieba@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi/peg: Fix Power Resource _ON and _OFFTim Wawrzynczak2022-07-131-5/+4
| | | | | | | | | | | | | | | | | The _ON and _OFF methods for the root port's power resource were calling the _ON and _OFF in the PEGP namespace, which was the incorrect method, it should have been NPON/NPOF, so this patch updates that. BUG=b:236676400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3653996329473f133e3f0d53306882dc3213b6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/acpi: Update GPIO polling methodTim Wawrzynczak2022-07-131-6/+14
| | | | | | | | | | | | | | The preferred way of polling in ACPI I've seen is usually to just divide the sleep into N chunks, and ignore the time taken in between. This works in practice (validated with Timer calls before and after). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a2cd82cea05c539eff30b9b9d6ef18550d17686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Modify NBCI _DSM subfunctionTim Wawrzynczak2022-07-131-1/+4
| | | | | | | | | | | | | | The NBCI "get callbacks" _DSM subfunction should utilize the same "get callbacks" subfunction from the GPS _DSM subfunction; this patch adds that Method call into the ACPI code. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf2f148b5a95acccb02f47cba1ef33a9fc16bcd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Keep track of dGPU power stateTim Wawrzynczak2022-07-131-1/+26
| | | | | | | | | | | | | | | To avoid extraneous calls from the kernel to _ON or _OFF, keep track of the power state of the GPU in an integer and exit _ON and _OFF routines early when attempting to enter the current state. BUG=b:236676400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Update FBVDD power-down delayTim Wawrzynczak2022-07-071-1/+1
| | | | | | | | | | | The EEs have observed the ramp down delay on this signal in more detail and 40 ms can still meet the sequencing requirements. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/{var/agah,acpi}: Update GPU GCOFF sequence for power downTim Wawrzynczak2022-06-241-9/+9
| | | | | | | | | | | | | | | | | We have clarified the powerdown sequence with Nvidia, and the EEs have come up with this modified sequence which still meets the requirements from the hardware design guide. BUG=b:233959099 TEST=Verified by ODM and EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya: Add GPS _DSM subfunction support for Nvidia GPUTim Wawrzynczak2022-06-083-0/+104
| | | | | | | | | | | | | | | | The _DSM subfunction for the Nvidia GN20 supports 1 additional subfunction, known as GPS, which is required to support GPU Boost. This implementation is minimal, essentially letting the GPU manage its own temperature. BUG=b:214581372 TEST=abuild Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Fix ACPI power sequencingTim Wawrzynczak2022-06-081-16/+23
| | | | | | | | | | | | Now that the power sequencing for the GPU is in a better shape, ensure that the ACPI code that performs power sequencing matches the C code that does the same. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Add support for NVPCF _DSM subfunctionTim Wawrzynczak2022-06-063-0/+75
| | | | | | | | | | | | | | | | The Nvidia GPU kernel driver supports another _DSM subfunction which is known as NVPCF (Nvidia Platform and Control Framework). The subfunction informs the kernel driver about Dynamic Boost parameters, which is done at init time, but can also be changed dynamically. BUG=b:214581372 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Add support for NBCI _DSM subfunctionTim Wawrzynczak2022-05-202-0/+82
| | | | | | | | | | | | | | | | | The Nvidia GPU supports another function named NBCI (NoteBook Common Interface), which has some subfunctions which are required for the Nvidia kernel driver to consume. The specification for this function comes from the Nvidia GN20 Software Design Guide. BUG=b:214581763 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya: Add PEG and initial Nvidia dGPU ASL supportTim Wawrzynczak2022-05-207-0/+710
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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