| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | mb/google/brya/variant/brya0: Add power limits for RPL SoC | Nick Vaccaro | 2022-10-05 | 1 | -0/+4 |
| * | src: Make PCI ID define names shorter | Felix Singer | 2022-03-07 | 1 | -5/+5 |
| * | mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurations | Tracy Wu | 2021-09-29 | 1 | -0/+1 |
| * | mb/google/brya/variants: fix override values for power limits | Sumeet Pawnikar | 2021-09-03 | 1 | -4/+5 |
| * | mb/google/brya: Fix PL4 limits | Tim Wawrzynczak | 2021-08-25 | 1 | -3/+3 |
| * | mb/google/brya/variants/brya0: add PL4 values for different SKUs | Sumeet Pawnikar | 2021-08-13 | 1 | -5/+5 |
| * | mb/google/brya/variants/brya0: set power limits for thermal | Sumeet Pawnikar | 2021-08-09 | 1 | -0/+18 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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