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* Revert "mb/google/brya/var/kinox: Configure TDC current"Dtrain Hsu2022-07-221-26/+0
| | | | | | | | | | | | | | | | | | | | | This reverts commit 58f68fb0cb8e9824256a115d1ebdc840c281e987. Reason for revert: ODM thermal team request that change IA/GT TDC current back to 20A. BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
* mb/google/brya/var/kinox: Override tdp pl1 valueDtrain Hsu2022-07-091-0/+4
| | | | | | | | | | | | | | Override tdp pl1 value to 30W in CPU MSR. BUG=b:238268367 TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts". Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya/var/kinox: Enable SaGvDtrain Hsu2022-07-071-0/+2
| | | | | | | | | | | | | Enable SaGv support for Kinox BUG=b:238153479 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id4646f1621a414a1ec4e272c826b0baea2bb4e19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Configure TDC currentDtrain Hsu2022-07-071-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | Configure TDC current for VR domains. +-----------+-------+-------+---------+-------------+----------+ | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | +-----------+-------+-------+---------+-------------+----------+ | IA | 2.8 | 2.8 | 80 | 43 | 28000 | +-----------+-------+-------+---------+-------------+----------+ | GT | 3.2 | 3.2 | 40 | 23 | 28000 | +-----------+-------+-------+---------+-------------+----------+ - IA TDC current from 20A to 43A. - GT TDC current from 20A to 23A. - Others comes from 'commit c6d716694272 ("soc/intel/alderlake: Configure the SKU specific parameters for VR domains")' BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie9cf8975309b57b4189e2b50f37bd61ac0105e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65659 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kinox: Support DPTF oem_variablesDtrain Hsu2022-07-072-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DPTF oem_variables and override based on charger type. BUG=b:230803675 TEST=1. With 90W adapter, check ACPI object ODVX and oem_variable[0]=1 Name (ODVX, Package (0x06) { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) 2. With 65W adapter, check ACPI object ODVX and oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I78929ecbc9db56aa234b3f46c641d1f2f3b7cba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya/var/kinox: Change HDMI port form DDPC to DDP2ericky_cheng2022-07-041-8/+9
| | | | | | | | | | | | | | | | | | | Modify GPIOs according to SOC_GPIO_Table_0629.xlsx. - GPP_A21 from TCP_DP1_CTRLCLK to NC - GPP_A22 from TCP_DP1_CTRLDATA to NC - GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1) - GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1) BUG=b:237468533 TEST=emerge-brask coreboot Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
* mb/google/brya/var/kinox: Modify ddi_ports_configDtrain Hsu2022-06-271-0/+7
| | | | | | | | | | | | | | | | | | | Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf. DDI_PORT_A = DP DDI_PORT_B = HDMI DDI_PORT_1 = Type-C DP DDI_PORT_2 = DP or HDMI BUG=b:233338341 TEST=Boot to Chrome OS and check all display port working Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Refactoring update_power_limits functionDtrain Hsu2022-06-221-34/+34
| | | | | | | | | | | | | | | | Based on 'commit 0b917bde36a7 ("mb/google/brya/var/kinox: Set power limit based on charger type")' to refactoring update_power_limits function for kinox. BUG=b:231911918 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1fcb593090f95bf23808e577dd11b8a836f47494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/kinox: Enable PCIe WLANIan Feng2022-06-222-0/+23
| | | | | | | | | | | | | | | | | | | | Enable PCIe WLAN for Kinox 1. Enable PCI port 5 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 2 for PCI port 5 BUG=b:236175551 TEST=Build and boot to OS in Kinox. Ensure that the WLAN module is enumerated in the output of lspci. localhost ~ # lspci 02:00.0 Network controller: Realtek Semiconductor Co., Ltd.Device c852 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I3fbeadc85c9c88f5d178326dbbc83762083fe59a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/brya/var/kinox: Set power limit based on charger typeDtrain Hsu2022-06-061-7/+68
| | | | | | | | | | | | | | | | | | | | | | | Set different power limit values using host command to detect charger type from ec. Scenario: 1. With 90W customized adapter, set to baseline. 2. With 170W customized adapter, set to performance. 3. With above 90W barrel jack/type-c adapter, set to performance. 4. With below 90W barrel jack/type-c adapter, set to baseline. BUG=b:231911918 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/brya/var/kinox: Update gpio configurationDtrain Hsu2022-06-051-4/+4
| | | | | | | | | | | | | | | | | Follow GPIO_Table_0527.xlsx to update gpio configuration. - Set GPP_A15 to NC. - Set GPP_A20 to TCP_DP1_HPD (native function1). BUG=b:225384873 TEST=Build and boot to Chrome OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/kinox: Set memory SMBus addresses based on board revDtrain Hsu2022-06-011-2/+10
| | | | | | | | | | | | | | | Starting with id 2, boards switched the memory SMBus slave address, and use 0x50, 0x52. BUG=b:233975373 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Add delay time for BH799BB rtd3Dtrain Hsu2022-06-011-0/+2
| | | | | | | | | | | | | | | | | | This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:232327947 TEST=Build and suspend_stress_test -c 2500 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Select VBT based on FW_CONFIGDtrain Hsu2022-05-313-0/+26
| | | | | | | | | | | | | Select vbt bin files based on DB_DISPLAY field of FW_CONFIG. BUG=b:233690293 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* mb/google/brya/var/kinox: Correct the target of DPTF active policyDtrain Hsu2022-05-301-4/+4
| | | | | | | | | | | | | | | Kinox has four temperature sensors. Modify the target of DPTF active policy to map correct temperature sensor. BUG=b:231380286 TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec comsole. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Set the physical location of each USB portDtrain Hsu2022-05-241-12/+10
| | | | | | | | | | | | | | | Set custom_pld of each USB port (both Type A and C) with actual physical location values. BUG=b:214025396 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ic84b9aae1501e36c2794382aabcf8225eef7783b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Update the DPTF parametersDtrain Hsu2022-05-241-2/+2
| | | | | | | | | | | | | | | | | | Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1 values. 1. Modify baseline PL1 min_power from 15000 to 12000. 2. Modify baseline PL1 max_power from 17000 to 25000. BUG=b:231380286 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kinox: Remove stop pin declaration for LANDtrain Hsu2022-05-191-4/+0
| | | | | | | | | | | | | | Remove the stop pin declaration for LAN. Confirmed with LAN vendor, 8111K do not need to implement stop pin. It caused S0ix fail. BUG=b:232327947 TEST=Build and suspend_stress_test -c 5 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Set memory SMBus addresses to 0x52, 0x50Dtrain Hsu2022-05-171-0/+7
| | | | | | | | | | | | | | | Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus addresses to 0x52, 0x50. BUG=b:231398371 TEST=Build and boot to OS with either 1 or 2 DIMM slots populated. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Disable thunderbolt interfaceDtrain Hsu2022-05-111-0/+4
| | | | | | | | | | | | | | | | | Disable all of the TBT devices in devicetree since kinox doesn't support thunderbolt. The change also need to disable TBT in fitimage (chrome-internal:4731094). BUG=b:231654363 TEST=Build and run on DUT. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya/var/kinox: Update power control settings for 15W SOCDtrain Hsu2022-05-021-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kinox keeps 65W barrel jack for Intel Pentium/Celeron SOC. Considering the dynamic loading of 65W adapter, it can up to 130% with 20ms. Update power settings to below for preventing blowing out the adapter. - Psys_Pmax 135W - PL2 39W - PL4 72.5W - Psys_PL2 65W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv For Intel Core processor, Kinox will use 90W barrel jack. Modify default power settings as below. - Psys_Pmax 135W - PL2 55W - PL4 123W - Psys_PL2 90W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6df2a17969067f8242519f7fd4ffd08a682fe3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hou-hsun Lee <hou-hsun.lee@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: set GPP_D0 to NCDtrain Hsu2022-03-311-0/+2
| | | | | | | | | | | | | | | | | Brask set GPP_D0 to GPO in commit b0769db4, but Kinox doesn't support fingerprint. This patch sets GPP_D0 to NC for matching schematic. BUG=b:214025396 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/kinox: Modify DDR4 to non-interleavedDtrain Hsu2022-03-222-0/+32
| | | | | | | | | | | | | | | Kinox is designed to 8-layer PCB. In order to reduce the length of memory singals, the DDR4 is designed from interleaved to non-interleaved. BUG=b:210094309 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* mb/google/brya/var/kinox: Reconfigure GPIO settingsDtrain Hsu2022-03-181-8/+4
| | | | | | | | | | | | | | | | | Configure GPIOs according to updated schematics. - GPP_A21 from NC to TCP_DP1_CTRLCLK. - GPP_A22 from NC to TCP_DP1_CTRLDATA. - GPP_E22 from DDIA_DP_CTRLCLK to NC. - GPP_E23 from DDIA_DP_CTRLDATA to NC. BUG=b:214025396 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Modify 15W SOC power control settingDtrain Hsu2022-03-172-0/+69
| | | | | | | | | | | | | | | | | | Modify 15W SOC default power settings for kinox. - PL2 39W - PL4 100W - Psys_PL2 65W - Psys_imax_ma 5000ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kinox: Enable PCIe-eMMC bridgeDtrain Hsu2022-03-162-2/+18
| | | | | | | | | | | | | | Enable PCIe-eMMC bridge for Kinox. BUG=b:218786363, b:211176722 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Modify the DPTF/Fan parametersDtrain Hsu2022-03-161-0/+141
| | | | | | | | | | | | | | Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters. BUG=b:221180425, b:222020226, b:221182596 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/kinox: update overridetreeDtrain Hsu2022-03-141-2/+213
| | | | | | | | | | | | | | 1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. BUG=b:218786363, b:214025396, b:212183045 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: update gpio settingsDtrain Hsu2022-03-022-0/+161
| | | | | | | | | | | | | Configure GPIOs according to schematics BUG=b:218786363 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Create kinox variantDtrain Hsu2022-02-153-0/+22
Create the kinox variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215049181 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KINOX Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I68cac421f6299a5f82f2ab51633173648c993060 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61789 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 05:30:03 +0000