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* mb/google/nissa: Remove GPP_B11 PAD configurationHarsha B R2022-07-131-2/+0
| | | | | | | | | | | | | | Remove the pad configuration for GPP_B11 as this is not used in Nereid/Nivviks BUG=b:227694137 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Don't put WLAN into D3coldReka Norman2022-07-081-6/+0
| | | | | | | | | | | | | | On nissa, WLAN should be a wake source, so don't put it into D3cold during suspend. BUG=b:233325709 TEST=Wake-on-WLAN works on nereid Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Lock gpio pins for nissa variantsEric Lai2022-07-051-5/+5
| | | | | | | | | | | | | | There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=check gpios are locked in pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa: Remove WLAN power sequencing workaroundReka Norman2022-06-301-4/+4
| | | | | | | | | | | | | | | | | | | CB:63368 added a workaround of driving EN_PP3300_WLAN_X low in bootblock to prevent a kernel crash on warm reboot. The crash has been fixed in the kernel, so remove the workaround. Kernel fix: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3463465/ BUG=b:225261075 TEST=Wifi works on nereid, warm reboot doesn't crash the kernel Change-Id: Idb5547e65ea934954326fcc740b14a83c939432e Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/nissa: Change pen garage wake to EV_ACT_DEASSERTEDEric Lai2022-06-281-1/+1
| | | | | | | | | | | | | | | | | Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed. After confirmed with the owner, the expect behavior is only wake when eject the pen. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/brya/variants/nereid: enable CNVi bluetooth in overridetreeJesper Lin2022-06-201-0/+8
| | | | | | | | | | | | | | | When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nereid overridetree to enable port 10. BUG=b:236162084 TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds without error. Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com> Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa: Increase I2C bus frequency to around 390 kHzReka Norman2022-06-151-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Set the speed to I2C_SPEED_FAST in each speed_config so that the speed_config is actually applied. Currently, the speed_config isn't applied, so the hcnt/lcnt calculation falls back to rise_time_ns and fall_time_ns, which are 0 since they're not set. This results in frequencies around 300 kHz. - Move the data hold time to the speed_config, ensuring that the resulting sda_hold value remains the same. - For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to give a frequency around 390 kHz. - In the baseboard, keep default scl_lcnt and scl_hcnt values. These work well for buses with a rise time around 100 ns, and can be used as a starting point before tuning them for a specific variant. BUG=b:229547183 TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks and nereid and check they meet the spec. nereid clock frequencies: I2C0 - 387.9 kHz I2C1 - 392.7 kHz I2C3 - 386.3 kHz I2C5 - 383.6 kHz nivviks clock frequencies: I2C0 - 387.67 kHz I2C1 - 380.47 kHz I2C2 - 388.51 kHz I2C3 - 384.03 kHz I2C5 - 389.09 kHz Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/nereid: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan2022-06-031-0/+52
| | | | | | | | | | | | | | | | | | | Nereid BUG=b:233030505 BRANCH=None TEST=Build FW and test on Nereid board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: I195f4b507ee57948751f0119735d8350dfce984b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
* mb/google/brya/var/nereid: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I47b069377046652ba4d278733a15bbca98bdb739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa: Change pen garage wake to EV_ACT_ANYEric Lai2022-05-211-1/+1
| | | | | | | | | | | | | | | Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed or inserted. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for NereidV Sowmya2022-05-201-0/+15
| | | | | | | | | | | | | | | | | | | | | | This patch configures external V1p05/Vnn/VnnSx rails for Nereid to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Rework LTE GPIO configurationReka Norman2022-05-191-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | Currently, the LTE pins are enabled in gpio.c, then disabled in fw_config.c if LTE is not present. However, since there's a short delay between mainboard_init() and fw_config_handle(), this means that when LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR sensor) will be floating for a short period of time. Rework the GPIO config so that the LTE pins are disabled in the baseboard, then enabled in fw_config.c for variants using LTE. However, this doesn't work for WWAN_EN and WWAN_RST_L since they need to be enabled in bootblock. So these are instead enabled in the variant gpio.c, then disabled in fw_config.c if LTE is not present. BUG=None TEST=LTE still works on nivviks Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/var/nereid: Enable OZ711LV2LN SD card controllerReka Norman2022-04-131-0/+6
| | | | | | | | | | | | | | | Select the Bayhub LV2 driver, and implement power sequencing as per the datasheet. BUG=b:223304542 TEST=Check that connecting an SD card works as expected in the OS. Probe the EN and RST signals and check the timing requirements are met. Change-Id: Id1cca2024e06e5b2c7cefd22aa0b735bc542dc3b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/var/nereid: Add WLAN power sequenceReka Norman2022-04-071-0/+15
| | | | | | | | | | | | | | | | | | | | | | | There are currently two issues related to the WLAN power sequencing on nereid: - If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck in S3. - During warm reboot, if we only assert RST without pulling the power low, then the kernel crashes. As a workaround while we investigate these issues, we pull the EN high in S5, then actively drive it low in bootblock and high in romstage to make sure it goes low during warm reboot. BUG=b:227694137, b:225261075 TEST=Cold boot succeeds, and there's no kernel crash during warm reboot. Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/brya/var/nereid: Enable pen garageReka Norman2022-04-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=None TEST=evtest works: Select the device event number [0-14]: 9 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153020.275201, -------------- SYN_REPORT ------------ Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153025.848689, -------------- SYN_REPORT ------------ Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153028.383195, -------------- SYN_REPORT ------------ Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153080.869155, -------------- SYN_REPORT ------------ Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMIReka Norman2022-04-072-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/brya/var/nereid: Add separate VBT for HDMIReka Norman2022-04-012-0/+13
| | | | | | | | | | | | BUG=b:226848617 TEST=HDMI works on nereid Cq-Depend: chrome-internal:4650256 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/var/nereid: Disable C1 PMC mux conn for HDMIReka Norman2022-04-011-1/+3
| | | | | | | | | | | BUG=b:226848617 TEST=HDMI works on nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1Reka Norman2022-04-012-1/+9
| | | | | | | | | | | | | | | | | C0 has no redriver, so enable SBU muxing in the SoC. C1 has a redriver which does SBU muxing, so disable SBU muxing in the SoC. However, this also disables AUX biasing when the pins are configured as NF6. So instead configure the C1 AUX bias pins as GPO. BUG=b:227259673 TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10Reka Norman2022-03-081-0/+1
| | | | | | | | | | | | | | | | | When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nivviks overridetree to enable port 10 instead of port 8, which is the external port used for bluetooth with PCIe WLAN. BUG=b:222595137 TEST=Bluetooth works on nivviks Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* mb/google/brya/var/nereid: Disable LTE-related GPIOsReka Norman2022-02-151-0/+18
| | | | | | | | | | | | | | Nereid does not support the LTE sub-board, so disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6d6b5babeefb7c4b79adab5e756f37616c2338d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/var/nereid: Initialise overridetreeReka Norman2022-02-151-2/+184
| | | | | | | | | | | | | | Add an initial overridetree for nereid based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I7d313439337c84ab1024b3570cc7b57b4255af5d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/var/nereid: Add H9JCNNNBK3MLYR-N6E for P1 buildReka Norman2022-02-153-0/+3
| | | | | | | | | | | | | | Nereid P1 will also use Hynix H9JCNNNBK3MLYR-N6E. Add it to the parts list and regenerate the memory IDs using part_id_gen. BUG=b:217096008 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibacb9dfb336967dd7fffe351d785cbbff9ba8b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya: Override memory ID to 0 for nivviks and nereid P0Reka Norman2022-02-032-0/+32
| | | | | | | | | | | | | | | | | | | In the nivviks and nereid pre-proto builds, the memory straps used don't match those generated by spd_tools. Each pre-proto build only supports a single memory part, and each of these parts should have ID 0 (see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code the memory IDs to 0 instead of reading them from the memory strap pins. From P1 onwards, the memory straps will be assigned based on the IDs generated by spd_tools. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya: Add SPD configs for nivviks and nereidReka Norman2022-02-033-0/+26
| | | | | | | | | | | | | | | | | | | | | | Add a mem_parts_used.txt for each of nivviks and nereid, containing the memory parts used in their pre-proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. nivviks: Micron MT62F1G32D4DR-031 WT:B nereid: Samsung K3LKBKB0BM-MGCP BUG=b:197479026 TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom contains an spd.bin. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya: Add GPIO table for nissaReka Norman2022-02-032-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | Fill in the nissa baseboard GPIO table based on the nivviks P0 and nereid P0 schematics. Also, add an override GPIO table for each of nivviks and nereid. The differences between nivviks and nereid are: - WFC: nivviks has a MIPI WFC and nereid has a USB WFC, so the MIPI-related pins are overriden to NC on nereid. - The DMIC pins and speaker I2S pins were swapped after nivviks P0. The baseboard reflects the new configuration, which will be used in nivviks P1 onwards, nereid, and future variants. For now, nivviks overrides the pins to the old configuration. Once nivviks P1 is released, this will need to be updated to handle both. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya: Add new baseboard nissa with variants nivviks and nereidReka Norman2022-01-043-0/+20
Add a new baseboard for nissa, an Intel ADL-N based reference design. Also, add variants for the two reference boards, nivviks and nereid. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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