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* mb/google/brya0: Enable CNVi DDR RFIM for brya0 variantRonak Kanabar2022-01-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for brya0 variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=b:201724512 BRANCH=None TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value. Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya: move SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to commonEric Lai2022-01-142-11/+1
| | | | | | | | | | | | | | ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem and prefetch mem. BUG=b:206739931 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: update overridetreeTony Huang2022-01-142-1/+288
| | | | | | | | | | | | | Init basic override devicetree based on initial schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Adjust CSE RO and Data partition in the CSE regionSridhar Siricilla2022-01-131-2/+2
| | | | | | | | | | | | | | | | | | The patch adjusts CSE region's internal partitions' (CSE RO and Data partition) sizes to match with sizes of MFIT generated CSE Region's internal partitions. BUG=b:213993778 TEST=Generate coreboot for Brya and verify with MFIT generated coreboot. Cq-Depend: chrome-internal:4452789 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Variants with ESx SoC use NEM for CARSubrata Banik2022-01-131-2/+2
| | | | | | | | | | | | | | | | | This patch ensures all brya variants with Alder Lake ESx SoC are using NEM by default for CAR set up. Default CAR configuration for QS SoC is eNEM. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/felwinter: Update ELAN touch HIDEric Lai2022-01-131-1/+1
| | | | | | | | | | | | | Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008. BUG=b:214010928 TEST=touch screen is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/taeko: Modify power sequence for SSD deviceKevin Chang2022-01-122-10/+32
| | | | | | | | | | | | | | | | In order to avoid having the FSP fail to detect the SSD device downstream of the RP, its PERST# must be deasserted earlier in the boot flow, therefore move PERST# deassertion to a romstage GPIO table. BUG=b:213828931 TEST=Build FW and run stress exceed 1000 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Move gpio_pm settings for brya variants to baseboardsTim Wawrzynczak2022-01-1215-134/+20
| | | | | | | | | | | | | | | The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/volmar: Generate SPD ID for supported partsDavid Wu2022-01-113-13/+22
| | | | | | | | | | | | | | | | | | | | | | Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=none TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic5b45ec83d0d7e0e1d16cb1afae501f06ee1f36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons2022-01-112-87/+1
| | | | | | | | | | | | | | Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Check if descriptor is writableAngel Pons2022-01-111-0/+30
| | | | | | | | | | | | | Copy the `is_descriptor_writeable()` function from the `intel/adlrvp` mainboard and use it in the `configure_pmc_descriptor()` function. With this change, this function is now identical for both mainboards. Change-Id: I2ff39682ed98c6b8bc60cc2218f36f4934b9903c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* mb/google/brya/bootblock.c: Sync cosmetics with adlrvpAngel Pons2022-01-111-16/+14
| | | | | | | | | | | | | | | Adjust the cosmetics of the `configure_pmc_descriptor()` function to match the code for the `intel/adlrvp` mainboard. The only difference is that adlrvp checks if the descriptor is writable. Tested with BUILD_TIMELESS=1, Google Brya0 remains identical. Change-Id: I9c524d5c422c765db200a15f484c2b8827ebd40b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* mb/google/brya: Restructure PMC descriptor updateAngel Pons2022-01-111-3/+6
| | | | | | | | | | | | | | Restructure the code in the `configure_pmc_descriptor()` so that it matches the code for the `intel/adlrvp` mainboard. This change does not reindent the contents of the original if-block intentionally as this will be taken care of in a reproducible follow-up. Change-Id: I8c9d9087cb2d0668f6a4afbb566d830bb9febd89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* mb/google/brya/(brya0,taeko): Use eNEM for CAR by defaultSubrata Banik2022-01-111-1/+1
| | | | | | | | | | | | | | | | More Brya variants like Brya0 and Taeko have migrated to use Alder Lake QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR by default for these variants. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63be166c8e428f052999fe29c8ebe1238e1a12ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* src/mainboard/google: Remove unused <acpi/acpi.h>Elyes HAOUAS2022-01-101-1/+0
| | | | | | | | Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/mainboard/google: Remove unused <console/console.h>Elyes HAOUAS2022-01-103-3/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I3a6a64273e3883942655272a544c41e90ef519fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/brask: Update PL and PsysPLCurtis Chen2022-01-101-0/+6
| | | | | | | | | | | | | | | | | | | | | Update all the ADL-P 15W/28W/45W SKU's PL and PsysPL. These config values are generated iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools: * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:211365920 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Enable SaGvRobert Chen2022-01-102-1/+3
| | | | | | | | | | | | | Enable SaGv support for vell BUG=b:208719081 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: I01e3da449e2cf53278f625ca265d09f7a1869ef7 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya: Create volmar variantDavid Wu2022-01-108-0/+46
| | | | | | | | | | | | | | | | | | Create the volmar variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:213127419 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VOLMAR Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5ebf62b7a17b075c0e28fb4e8b7c501fc8db3ea3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/agah: move memory makefile to correct pathTony Huang2022-01-104-33/+27
| | | | | | | | | | | | | Move memory Makefile.inc and dram_id.generated.txt to correct path BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: Ib5d9d9dd6f881f0b9cf2736809a74e5045c3c217 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Use genesyslogic gl9755 SD card reader for FelwinterEric Lai2022-01-101-0/+1
| | | | | | | | | | | | | | Felwinter selects DRIVERS_GENESYSLOGIC_GL9755 Kconfig to make use of SD card reader driver. BUG=b:209501017 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I196ae9c5dbbcc6057d17605eece27563bcc79af8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60893 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: Add MIPI camera infoShon Wang2022-01-073-0/+73
| | | | | | | | | | | | | | Add OVTI8856 information for vell: BUG=b:210801553 TEST=Build and boot on vell Change-Id: I43de859cd0cdd9fe21c16cabfad511ed0b368ee3 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/vell: Swap TPM I2C with touchscreen I2CShon Wang2022-01-073-8/+29
| | | | | | | | | | | | | | | | According to the latest schematic for the next build phase, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:210572663 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: If72717a2c073f5b871c3109399f466a04a9d2484 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/taniks: Change probe for audio 4 channel speakerJoey Peng2022-01-072-5/+5
| | | | | | | | | | | | | | Taniks only uses 4 channel speakers. Change the probe name to match SOF topology settings. BUG=b:207808510 TEST=dmidecode -t 11 shows correct audio fw_config. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2986bd212cef47f70dfeedc642a8db3314c947f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix: Tune I2c frequencyWisley Chen2022-01-071-0/+18
| | | | | | | | | | | | | | | | | | | Tune the I2c frequency I2C0 - 391 kHz I2C1 - 391 Khz I2C2 - 393 kHz I2C3 - 394.7 KHz I2C5 - 399.6 KHz BUG=b:213298209 TEST=build Change-Id: Id15c5298f8917bac404026f1ecb000fa7f925416 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/anahera: Fine tune I2C frequencyWisley Chen2022-01-071-0/+12
| | | | | | | | | | | | | | | | | Fine tune i2c frequency. I2C0 - 399.6 kHz I2C1 - 391.4 kHz I2C3 - 398.1 kHz I2C5 - 399.9 kHz BUG=b:213295817 TEST=build Change-Id: I9a89820a8d9ae4c9b4ee499e8467426e0670656d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/anahera: Swap TPM I2C with touchscreen I2CWisley Chen2022-01-073-25/+21
| | | | | | | | | | | | | | | According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:212465011 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I1bb1857b4c5b06ca4ad660bf73e0c4df9c376a58 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/anahera{4es}: Correct WWAN power sequenceWisley Chen2022-01-075-2/+40
| | | | | | | | | | | | | Correct the WWAN power sequence to meet spec BUG=b:213021172 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Iab221fd03c637c82f6ce5c8278d432decf1b30c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/anahera{4es}: Correct SSD power sequenceWisley Chen2022-01-074-2/+36
| | | | | | | | | | | | | M.2 spec describes PERST# should be sequenced after power enable. BUG=b:213021171 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I66345d985f4db4f13b23c0a21c179835908b6574 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/brask: Change TPM I2C to I2C1Zhuohao Lee2022-01-075-27/+29
| | | | | | | | | | | | | | | The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch moves the TPM I2C setting from the board layer to the baseboard and fixes the TPM I2C bus assignment. BUG=b:211886429 TEST=build pass Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60439 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anahera{4es}: Add Chrome OS privacy screen _HIDTim Wawrzynczak2022-01-062-0/+4
| | | | | | | | | | | Similar to commit 0167f5adb (mb/google/redrix: Add _HID for privacy screen device), add the same _HID to the privacy screen device. Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* mb/google/brya/var/agah: Add new memory supportTony Huang2022-01-063-11/+45
| | | | | | | | | | | | | Do initial memory support for project agah BUG=b:210970640 TEST=FW_NAME=agah emerge-brya coreboot Change-Id: Iaeea12a9dd8110a499b5df4de89dc1f74b88a580 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Create agah variantTony Huang2022-01-068-0/+46
| | | | | | | | | | | | | | | | | | Create the agah variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:210970640 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AGAH Change-Id: I6adcf4e8010969cf185513d68bb1b76ea08194c7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields.Joey Peng2022-01-052-8/+0
| | | | | | | | | | | | | | Since fw config fields for DB_SD can share the same driver, we will remove the duplicate fields DB_SD_GL9750 and DB_SD_RTS5232S. BUG=b:212240358 TEST=emerge-brya coreboot and can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/primus: Fix some GPIO programmingAriel Fang2022-01-052-4/+16
| | | | | | | | | | | | | | | | | | | After checking them against schematics, a few unused GPIOs that were inherited from the baseboard were missed, so this CL programs them as PAD_NC. GPP_B2 => non-use GPP_B15 => non-use (for FPR) GPP_D3 => non-use (Test point) GPP_E21 => non-use (for LCLW Detect) BUG=b:211721639 TEST= USE="project_primus" emerge-brya coreboot Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/brya/(anahera,primus): Use eNEM for CAR by defaultSubrata Banik2022-01-051-1/+1
| | | | | | | | | | | | | | | | | More Brya variants like Anahera and Primus have migrated to use Alder Lake QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR by default for these variants. BUG=b:168820083 TEST=Able to build and boot primus variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I65d12de08adf85140976e1a7659ad7b684aa75c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/kano: Add stylus probeDavid Wu2022-01-041-1/+7
| | | | | | | | | | | | | | | Kano has non-stylus sku. Add a FW_CONFIG field to indicate stylus presence and add a probe statement to the devicetree for the corresponding device. BUG=b:208179467 TEST=non-stylus doesn't register garage driver. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24839c39280185a6d649a82dd9f025ee305c2eed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kano: Enable stylus pen powerDavid Wu2022-01-041-0/+2
| | | | | | | | | | | | | Set GPP_D16 (PEN_PWR_EN) to output high. BUG=b:195853169 TEST=build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I25b6d1a40ed0939b303a03984cb0087fb6cab4d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Add new baseboard nissa with variants nivviks and nereidReka Norman2022-01-0414-0/+179
| | | | | | | | | | | | | | | | | | Add a new baseboard for nissa, an Intel ADL-N based reference design. Also, add variants for the two reference boards, nivviks and nereid. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMCKevin Chang2022-01-041-2/+12
| | | | | | | | | | | | | | | | | | | Taeko will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:211914322 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend: chromium:3358662 Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/mb: Remove unused <string.h>Elyes HAOUAS2022-01-042-2/+0
| | | | | | | | | Change-Id: I5f2710b2034882a24a041d99e37ec364193d85e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/brya/var/taeko: Modify DPTF setting for taekoKevin Chang2022-01-042-36/+36
| | | | | | | | | | | | | | | The new settings from the thermal team improve performance mainly with respect to fan control settings. BRANCH=None BUG=b:212210824 TEST=Built and tested on taeko board Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next buildKevin Chang2022-01-043-30/+34
| | | | | | | | | | | | | | Taeko is going to exchange i2c port for touchscreen and cr50. BUG=b:211911780 TEST=build pass Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kano: Set vGPIO reset typeDavid Wu2022-01-041-20/+20
| | | | | | | | | | | | | | | Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207527331 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/anahera: Add new memory supportWisley Chen2022-01-046-8/+24
| | | | | | | | | | | | | | | | | Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212328327 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ib08a1348333accdbb7551ef428d8d130b621dd9f Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix: Add new memory supportWisley Chen2022-01-046-8/+24
| | | | | | | | | | | | | | | | | Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212330664 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I32491f86813c8e6566774d4b3d7d82295f906bd3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update overridetree for DPShon Wang2022-01-041-34/+38
| | | | | | | | | | | | | update override devicetree for type-c display based on schematics BUG=b:209489126 TEST=emerge-brya coreboot Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Icd2f5de38df0eb89fb92ea2abe25851c0d6ec53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/brask: Change I2C/DDC signalsRory Liu2022-01-032-14/+14
| | | | | | | | | | | | | | | The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14, I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12. BUG=b:206602609 TEST=build pass Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/google/brya/var/gimble: Update Slow Slew RateMark Hsieh2022-01-031-2/+2
| | | | | | | | | | | | | | - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* src: Remove duplicated includesElyes HAOUAS2022-01-011-1/+0
| | | | | | | | Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 18:31:44 +0000