| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | sb/intel: Use `bool` for PCIe coalescing option | Angel Pons | 2022-01-04 | 1 | -1/+1 |
| * | mb/google/jecht: Use Haswell CPU code | Angel Pons | 2021-01-24 | 1 | -1/+4 |
| * | soc/intel/broadwell: Separate PCH in devicetree | Angel Pons | 2020-10-30 | 1 | -2/+2 |
| * | mb/google/jecht: Prepare devicetree for PCH split | Angel Pons | 2020-10-30 | 1 | -91/+94 |
| * | broadwell: Factor out PIRQ routing from devicetree | Angel Pons | 2020-07-28 | 1 | -9/+0 |
| * | mb/*/*/devicetree.cb: Normalize disabled PIRQ values | Angel Pons | 2020-07-26 | 1 | -4/+4 |
| * | mb/google/{beltino,jecht}: Drop SIO configuration lines | Nico Huber | 2020-01-07 | 1 | -4/+0 |
| * | mb/google,samsung/*: Add LPC TPM chip driver to devicetree | Matt DeVillier | 2018-08-01 | 1 | -0/+3 |
| * | Combine Broadwell Chromeboxes using variant board scheme | Matt DeVillier | 2016-12-22 | 1 | -3/+6 |
| * | google/jecht: add new mainboard | Patrick Georgi | 2015-06-09 | 1 | -0/+122 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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