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* mb/gogle/skyrim/devicetree: enable crypto deviceFelix Held2022-05-211-0/+1
| | | | | | | | | | | | | | | | | | | | The crypro device on bus A device 0 function 2 wasn't enabled, so it didn't get resources assigned resulting in this the Linux kernel error: [ 38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device] [ 38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002) [ 38.582175] ccp 0000:04:00.2: ioremap failed [ 38.582178] ccp 0000:04:00.2: initialization failed [ 38.582181] ccp: probe of 0000:04:00.2 failed with error -12 Enable the crypto device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/skyrim: Add better descriptors for USB endpointsJon Murphy2022-05-201-4/+4
| | | | | | | | | | | | | | Fix descriptors for USB ports to align with their function and placement with respect to the schematics. BUG=N/A TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: allow MKBP devices and disable TBMC deviceIan Feng2022-05-121-2/+2
| | | | | | | | | | | | | | | | | Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:230682161 TEST=manual test on Skyrim: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/skyrim/var/skyrim: Add USB WWAN configurationKarthikeyan Ramasubramanian2022-05-121-1/+1
| | | | | | | | | | | | | | | | | | Add Fibcom FM101-GL USB WWAN configuration with the required power sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is enumerated in the output of lsusb. localhost ~ # lsusb Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/skyrim: Add VL822 USB hubKarthikeyan Ramasubramanian2022-05-121-12/+0
| | | | | | | | | | | | | | | | In Skyrim, USB-A port and WWAN modules are connected to the SoC USB ports through an external hub. Update the USB configuration in the devicetree accordingly. Enable the ACPI driver for external USB hub. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports are enumerated correctly in the output of lusub command. Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Fix SD card power sequenceIan Feng2022-05-051-0/+2
| | | | | | | | | | | | | | Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Configure SD_AUX_RESET_L signalIan Feng2022-04-271-1/+1
| | | | | | | | | | | | | | | | | Set native function (SD_AUX_RESET_L), and drive it high. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Include smm handlerRaul E Rangel2022-04-272-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to include the SMM handler to enable SCI events when ACPI is enabled. With this enabled we now see we have EC timeout problems while in SMI: [SPEW ] SMI# #1 [WARN ] SMIx88 => 0x800 [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000 [DEBUG] Chrome EC: UHEPI supported [ERROR] Timeout waiting for EC QUERY_EVENT! [DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. [ERROR] EC returned error result code 1 [DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb We still need to debug that. I suspect we have problems reading from the ACPI IO decodes 0x62 or 0x66. BUG=none TEST=Verify SMI handler runs Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/skyrim: Fix eSPI configurationJon Murphy2022-04-272-2/+2
| | | | | | | | | | | | | | | | | * Use GPE 24 since it doesn't conflict with any existing GEVENTS. * Remove IRQ 12 mapping since it's not used. * Unmask IRQ1 in PM registers. * Use the new SMITYPE_ESPI_SCI_B SCI. BUG=b:227282870 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Prepare for enabling PSP verstageKarthikeyan Ramasubramanian2022-04-251-0/+1
| | | | | | | | | | | | | Add various verstage init functions to prepare for enable PSP verstage. BUG=None TEST=Build Skyrim BIOS image with PSP verstage enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d0dba05d4d083e2c6860078676e59cf8f487c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Add Goodix touchscreenIan Feng2022-04-191-4/+4
| | | | | | | | | | | | | Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:228907558 TEST=local build and tested with Goodix touch screen Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD deviceChris.Wang2022-04-061-0/+6
| | | | | | | | | | | | | | | | | Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim, clock source 0/1/2 are routed for WLAN/SD/SSD device. BUG=b:227297986 BRANCH=none TEST=Build Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Fix ESPI communication issuesKarthikeyan Ramasubramanian2022-04-021-2/+2
| | | | | | | | | | | | | | | | | | | | * Use dedicated ALERT pin to resolve NO_RESPONSE error/status while getting target configuration. * Configure the ESPI to operate at 16 MHZ since operating at 33 MHz causes boot stall. BUG=b:226635441 TEST=Build and Boot to OS in Skyrim. Ensure that EC <-> AP communication is working fine through Host Command debug logs in EC console, ectool version command. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/63286 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Implement mb_set_up_early_espiRaul E Rangel2022-03-282-0/+26
| | | | | | | | | | | | | This will setup the eSPI GPIOs in bootblock right before eSPI init. BUG=b:226635441 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BLRaul E Rangel2022-03-281-10/+10
| | | | | | | | | | | | | | | | | The eSPI CS function only exists on AGPIO30. We will need to rework all boards to make eSPI function. I also fixed the comments on the other eSPI pins. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Add DXIO descriptorsJon Murphy2022-03-272-2/+7
| | | | | | | | | | | | | | Add Skyrim DXIO descriptors using info from AMD and skyrim bouard shematics. BUG=b:225179599 TEST=Boots to OS on Skyrim Board Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Fix Backlight GPIOJon Murphy2022-03-231-1/+1
| | | | | | | | | | | | | | | Backlight GPIO was set to HIGH, when it should have been set LOW to enable the backlight in the embedded display. BUG=b:224618411 TEST=load on Skyrim proto1, observe backlight Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLEDFelix Held2022-03-191-0/+2
| | | | | | | | | | | | | | Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, PSPP will be reenabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/skyrim: Fix I2C voltagesRaul E Rangel2022-03-181-0/+6
| | | | | | | | | | | | | | | Needed so i2c communication works. BUG=b:224618411 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable tis_plat_irq_statusRaul E Rangel2022-03-183-1/+14
| | | | | | | | | | | | | | | This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:224618411 TEST=Compile skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2Felix Held2022-03-141-1/+1
| | | | | | | | | | | | | The one USB2 port on the XHCI2 controller should have the port ID 2.0, since it's the first USB2 port on that XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Configure WLANJon Murphy2022-03-104-4/+35
| | | | | | | | | | | | | | Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mappping derived from Skyrim schematic. BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim:Update GPIO 32Jon Murphy2022-03-101-1/+1
| | | | | | | | | | | | | | | GPIO 32 was not allocated correctly, updating to reflect the native function use of the pin BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable PCIe devices in devicetreeJon Murphy2022-02-281-0/+5
| | | | | | | | | | | BUG=b:214414301 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Enable AP <-> D2 communicationJon Murphy2022-02-283-1/+49
| | | | | | | | | | | | | | | | Configure D2 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for D2 device and enable the required config items. BUG=b:214414776 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Add eSPI configurationJon Murphy2022-02-281-0/+38
| | | | | | | | | | | BUG=b:214413613 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Add initial I2C configurationJon Murphy2022-02-281-0/+7
| | | | | | | | | | | | | | Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:214414677 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Log mainboard events to elogJon Murphy2022-02-281-0/+6
| | | | | | | | | | | | BUG=b:214414851 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Add ACPI configuration for USB portsJon Murphy2022-02-281-2/+71
| | | | | | | | | | | | | | | | | | | The USB port configuration was derived from the PPR and schematics. This board has 6(some multi-purpose) ports. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras 1 Bluetooth transceiver BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Enable USB controllers in devicetreeJon Murphy2022-02-261-0/+4
| | | | | | | | | | | BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable internal graphicsJon Murphy2022-02-261-0/+3
| | | | | | | | | | | | BUG=b:214416935 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Enable console UARTJon Murphy2022-02-261-0/+1
| | | | | | | | | | | | BUG=b:214414501 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Add smihandlerJon Murphy2022-02-264-0/+42
| | | | | | | | | | | | | BUG=b:214415408 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable Chrome ECJon Murphy2022-02-262-0/+85
| | | | | | | | | | | | BUG=b:214413613 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable ACPI tablesJon Murphy2022-02-261-0/+5
| | | | | | | | | | | | | | | Add GPIO initialization and ACPI generation for tables BUG=b:214415303 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: First pass GPIO configuriation for SkyrimJon Murphy2022-02-251-1/+133
| | | | | | | | | | | | | BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Add stubs to configure GPIOsJon Murphy2022-02-244-0/+61
| | | | | | | | | | | | | BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Add new mainboardKarthikeyan Ramasubramanian2022-02-033-0/+17
Skyrim is a new Google mainboard with AMD Sabrina SOC. BUG=b:214413553 TEST=util/abuild/abuild -t GOOGLE_SKYRIM --clean Change-Id: I008fea4aa163b8aa66e86735b29b3fdc4e08a327 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 03:41:06 +0000