summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google/skyrim/variants/baseboard
Commit message (Collapse)AuthorAgeFilesLines
* mb/google/sarien to zork: Rename Makefiles from .inc to .mkMartin Roth2024-01-241-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib8a2ae26ed4380592d15e1a7b2d682639413af01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* mb/google/skyrim: Update DXIO descriptor definitionJon Murphy2023-12-264-6/+85
| | | | | | | | | | | | | | | | | Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mainboard/google/skyrim: Enable wake-on-DPRobert Zieba2023-09-211-1/+2
| | | | | | | | | | | | | | | | Enable wake-on-DP by adding USB mux events to the wake mask. The EC wakes the AP with these events for DP connect/disconnect. BUG=b:294307786 TEST=DP connect/disconnect wakes the DUT appropriately. Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google: Remove space between function name and '('Elyes Haouas2023-09-111-1/+1
| | | | | | | | Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim: Set i2c3 to hidden in devicetreeMatt DeVillier2023-09-071-1/+1
| | | | | | | | | | Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Add SPDX license headers to MakefilesMartin Roth2023-08-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki2023-07-142-12/+0
| | | | | | | | | | | | | | | | | | It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki2023-07-061-2/+2
| | | | | | | | | | | | | | | | | tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/: Set system_configuration to 3 to avoid SMU callJason Glenesk2023-06-281-2/+4
| | | | | | | | | | | | | | | | | | | | Update system_configuration to 3 for 15W. Specification "FT6 Infrastructure Roadmap #57316" incorrectly lists system config index of 4 for 15W. Setting to 4 will cause an additional call to the SMU that is not needed and will add boot delay. Both SMU and FSP interpret configs > 3 as 3. BUG=b:267294958 TEST=Confirm extra message "Service Request 0x5F" not in log. Change-Id: I1f3e305c48801b4e499de56d06c0dcd3eeacc626 Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76091 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetreeFelix Held2023-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim: Add common_config.acp_configTim Van Patten2023-05-311-0/+7
| | | | | | | | | | | | | | | | | | Add 'common_config.acp_config' to the device tree, so we have the correct pin configuration. BUG=b:225320579 TEST=USE=fwconsole emerge-skyrim ... ; verify 'devbeep' works in depthcharge console TEST=Boot into ChromeOS, verify YouTube sound works with internal speakers and headphone jack TEST=Boot into ChromeOS, verify microphone with Google Meet Change-Id: Ie2d79408104273d8a53214b683800fa0663c14d3 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Enable DmaProperty on WLAN deviceMark Hasemeyer2023-05-221-0/+1
| | | | | | | | | | | | | | | | Set the DmaProperty in the device's _DSD so that the OS can treat the device as untrusted. BUG=b:278310256 TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1 iperf3 -c <iperf3-server> -t 60 (No performance regressions seen) Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/google/skyrim: Remove unused sleep GPIO tableKarthikeyan Ramasubramanian2023-04-053-20/+0
| | | | | | | | | | | | | | | On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function overhead. BUG=None BRANCH=Skyrim TEST=Build Skyrim BIOS image. Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/skyrim: Remove todo about BT controller timeoutsMartin Roth2023-03-221-1/+0
| | | | | | | | | | | | | | | | This will be tracked directly in the bug, so a code comment is not needed. BUG=263161283 TEST=none BRANCH=Skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4d5af35762354c8825d30f813098547a7e009e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73828 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim: Delete PSPP TODOMartin Roth2023-03-211-1/+2
| | | | | | | | | | | | | | | | | | Because Mendocino doesn't support PCIe Gen4, PSPP on this platform does not save any power, so leave it disabled. BUG=273889287 TEST=None BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1a1c6692cd0a44469a35582042b92eeec31073fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: override winterhold PCIe configMartin Roth2023-03-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Winterhold boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/skyrim: Allow port descriptors to be overriddenMartin Roth2023-03-091-0/+3
| | | | | | | | | | | | | | | | This allows variants to override the skyrim port descriptors. BUG=None TEST=Tested with following patches BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/skyrim: Move SPL setting to variantsChris Wang2023-03-071-2/+0
| | | | | | | | | | | | | | | | Move the sustained_power_limit_mW setting from the baseboard to variants. This setting will be needed before STT is enabled, but once STT is enabled, this setting should be removed. BUG=b:265267957 BRANCH=none TEST=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I7b9779600cfa8c7581732e936a714728fd618d20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang2023-03-041-0/+1
| | | | | | | | | | | | | | | | The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten2023-03-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/*: Resume from suspend on critical batteryIvan Chen2023-02-221-1/+3
| | | | | | | | | | | | | | | | | | | | | This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/skyrim: Configure GPIO 67 as an unused GPIOMartin Roth2023-02-091-2/+2
| | | | | | | | | | | | | | | | | GPIO 67 is not currently used on skyrim, so set it as no-connect. Since it's now free for other purposes, make sure that the SPI-ROM-SHARING functionality is disabled. BUG=b:268330591 TEST=Examine registers after change Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes2023-02-041-1/+2
| | | | | | | | | | | | | | | | | | Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:266696987 BRANCH=None TEST=Observe kernel ec panic handler run when ec panics Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/google/skyrim/baseboard/devicetree: enable mp2 deviceFelix Held2023-01-251-0/+1
| | | | | | | | | | | | | | | | | | The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. An equivalent change was verified on Chausie. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Fix Bluetooth configurationKarthikeyan Ramasubramanian2022-12-211-1/+6
| | | | | | | | | | | | | | | | Power resource for Bluetooth device is not configured correctly in the device tree. Fix Bluetooth devicetree configuration. BUG=b:262785310 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able to connect to a Bluetooth headset. Change-Id: Id980424349537be35860dec04cc823d419cefe2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable PCIe RTD3 supportJasonNien2022-12-141-1/+7
| | | | | | | | | | | | | | | | Add PCIe RTD3 support for Skyrim BUG=b:245550573 TEST=Boot/Reboot cycles and Suspend_stress_test 10 times Signed-off-by: JasonNien <finaljason@gmail.com> Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/guybrush,skyrim: use gpio.h include everywhereFelix Held2022-12-132-4/+2
| | | | | | | | | | | | Now that gpio.h will only include the defines in the IASL case, gpio.h can be included instead of soc/gpio.h in the files that will be directly or indirectly included in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: use gpio.h includeFelix Held2022-12-106-4/+6
| | | | | | | | | | | | | | | | Replace the amdblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h in the AMD SoC case. Since baseboard/ec.h and indirectly baseboard/gpio.h files will get included in the DSDT, the soc/gpio.h includes in those aren't replaced with a gpio.h include for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Move common DPTC values to devicetree.cbTim Van Patten2022-11-291-0/+18
| | | | | | | | | | | | | | | The Skyrim devices share a common set of DPTC values to enable booting with low/no battery. Rather than duplicating them in each variant's overridetree.cb, move them into the baseboard/devicetree.cb. BUG=b:217911928 TEST=tast run <IP> power.ShutdownWithCommandBatteryCutoff Change-Id: I20f0a8259c2fc986da23026da88feadd69942046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69904 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Pass Ti50 IRQ to PSPMark Hasemeyer2022-11-221-1/+1
| | | | | | | | | | | | | | | | | | | | | It shouldn't be assumed that all variants of skyrim will use the same gpio for TPM interrupts. Use the PSP's new mailbox command to tell it what gpio the tpm interrupt comes in on. BUG=b:248193764 TEST=tast run <ip> hwsec.TPMContest Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK Use incorrect GPIO in mailbox cmd and verify TPMContest test failed. Signed-off-by: Mark Hasemeyer <markhas@google.com> Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Implement touchscreen power sequencingMatt DeVillier2022-10-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | Assuming variants have a touchscreen by default, set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. BUG=b:121309055 TEST=build/boot skyrim with rest of patch series Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQFrank Wu2022-10-221-1/+1
| | | | | | | | | | | | | | | | The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/skyrim: Allow variants to override romstage GPIO tableMatt DeVillier2022-10-132-2/+11
| | | | | | | | | | | | | Switch from gpio_configure_pads() to gpio_configure_pads_with_override() so variants can override romstage GPIO defaults. Rename baseboard function and add an weak empty override function to be used by variants. Will be used for touchscreen power sequencing in a follow-on commit. Change-Id: I45586237919cd07a171beac57f3510e26338f67f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Rename pcie_gpio_table to romstage_gpio_tableMatt DeVillier2022-09-282-7/+8
| | | | | | | | | | | | | Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Rename the getter function to match. Change-Id: I285602209072247895c2cb0830f3faf675328757 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim: rename baseboard GPIO table getter for clarityMatt DeVillier2022-09-282-9/+4
| | | | | | | | | | | | | | Rename variant_base_gpio_table() to baseboard_gpio_table(), since the GPIO table comes from the baseboard, and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. Change-Id: Icebf7e11736929389227063039575a4c5ecf3840 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/skyrim/var/winterhold: Bug fix, modify GXTP7863 irq settingEricKY Cheng2022-09-261-1/+1
| | | | | | | | | | | | | Modify GXTP7863 generic.irq to generic.irq_gpio. BUG=b:245082617 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Iaf6cc6010132d5b33b06909ceb1069115a911b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Remove elog_gsmi_cb_mainboard_log_wake_sourceRaul E Rangel2022-09-021-5/+0
| | | | | | | | | | | | | | | | | | | elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. This is a copy of CB:63280 but for skyrim. BUG=b:227163985, b:243557044 TEST=suspend/resume skyrim and no longer see EC wake sources in elog. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iac56840fe15101bc556d8cce9960f761c6ea7181 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/skyrim: Move I2C config to devicetreeJon Murphy2022-08-171-0/+26
| | | | | | | | | | | | | | | | The I2C config was unnecessarily placed in the overridetree. As we prepare for fanout, this is going to cause unnecessary noisy changes. Move the I2C config to the devicetree to avoid this. BUG=None TEST=Build Change-Id: I09ad5c911a0fd00274761cb71e9b659b47cd6da1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66802 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Rename Sabrina to MendocinoJon Murphy2022-08-111-2/+2
| | | | | | | | | | | | | | | | | | | | | 'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarityRaul E Rangel2022-08-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default state for the IRQ lines when the eSPI controller comes out of reset is high. This is because the IRQ lines are shared with the other IRQ sources using AND gates. This means that in order to not cause any spurious interrupts or miss any interrupts, the IO-APIC must use a low polarity trigger. On zork/guybrush/skyrim the eSPI IRQs are currently working as follows: * On power on/resume the eSPI controller drives IRQ 1 high. * eSPI controller gets configured to not invert IRQ 1. * OS configures IO-APIC IRQ 1 as Edge/High. * EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1 high. * eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ 1 as high. This results in missing the first interrupt. * When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the eSPI controller to set IRQ1 to low. We are now primed to catch the next edge high interrupt. This is generally not a problem since the linux driver will probe the 8042 with interrupts off. On S3/S0i3 resume since the eSPI controller comes out of reset driving the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is configured to trigger on edge high. This results in the 8042 controller getting incorrectly marked as a wake trigger. By configuring the IO-APIC to use low polarity interrupts, we no longer lose the first interrupt. This also means we can use a level interrupt to match what the EC actually asserts. We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI because the linux kernel will ignore the level/polarity parameters for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't have this problem. The PIC is not currently configured anywhere and it defaults to an edge/high trigger. We could add some code to configure the PICs trigger register, but I don't think we need the functionality right now. For zork and guybrush, this change is a no-op. eSPI is configured in verstage which is located in RO, and we have already locked RO for these devices. We will need to figure out how to properly set the `vw_irq_polarity` for these devices. BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104 TEST=On zork, guybrush and skyrim $ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count' Verify keyboard works as expected and no interrupt storms are observed. On morphius I verified keyboard and mouse work on windows as well. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Resolve boot behaviorJon Murphy2022-08-071-0/+2
| | | | | | | | | | | | | | | Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices will be initialized in time for the nominal boot flow. BUG=b:237701972 TEST=Boots to OS BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/google/skyrim/baseboard: Enable Wake-On-LAN functionalityRobert Zieba2022-07-201-2/+4
| | | | | | | | | | | | | | | | The generic wifi driver currently contains a lot of intel-specific functionality that interferes with enabling wake-on-lan. This commit changes the device tree to use the generic PCIe driver which better supports this functionality. BUG=b:237682766 TEST=Booted on skyrim device and verified that wake on LAN works Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable fingerprint sensor in SkyrimMoises Garcia2022-06-291-1/+1
| | | | | | | | | | | | | | | | | Add fingerprint device and select UART_ACPI driver. Disable FPMCU until the proper boot segment initializes it. BUG=b:228271993 BRANCH=NONE TEST=Can add fingerprints and unlock the device using them. Signed-off-by: Moises Garcia <moisesgarcia@google.com> Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Add SoC thermal zoneFred Reitberger2022-06-281-0/+54
| | | | | | | | | | | | | | | The temperature values were taken from guybrush as a starting point for skyrim. BUG=b:230428864 TEST=Boot skyrim to OS and verify thermal zones are populated and working in /sys/class/thermal/ Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6669b32f5e3dd63c6523f74166089eb4eb2d7848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/variants/baseboard: enable iommuJason Glenesk2022-06-221-0/+1
| | | | | | | | | | | | | | | | | | With IOMMU disabled, kernel complains that 'IOMMUv2 functionality not available on this system'. Enable iommu in devicetree for skyrim proto board in order to allow kernel to load and initialize IOMMUv2. BUG=b:232750390 TEST=Boot to Chrome OS on skyrim board, and grep dmesg for "AMD IOMMUv2 loaded and initialized" Change-Id: I2f10f5eda8083335619a34c44df253b8e5a8572c Signed-off-by: Jason Glenesk <Jason.Glenesk@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/google/skyrim: Add ACPI _PLD custom valuesWon Chung2022-06-071-4/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | | | +----------------+ BUG=b:232298017 TEST=None Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Idca3dd468f1b9fde37a1bbf20d65768032c7160b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/skyrim/var/skyrim: Add audio codec and amp supportIan Feng2022-06-071-1/+1
| | | | | | | | | | | | | | | | Add two combination: 1. ALC5682I-VS and ALC1019 2. NAU88L25 and MAX98360 BUG=b:227165780, b:228879074 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim/baseboard/devicetree: enable S0ixFelix Held2022-05-241-0/+2
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6c5b3f83b66a2d54611ada3cb97ddda4b655d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64606 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/gogle/skyrim/devicetree: enable display HDA deviceFelix Held2022-05-211-0/+1
| | | | | | | | | | | The HD audio controller of the GPU on bus A device 0 function 1 wasn't enabled, so it didn't get resources assigned. Enable it to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/gogle/skyrim/devicetree: enable audio coprocessor deviceFelix Held2022-05-211-0/+1
| | | | | | | | | | | The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't get resources assigned. Enable the ACP device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 06:22:08 +0000