| Commit message (Collapse) | Author | Age | Files | Lines |
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After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.
BUG=b:213403891
BRANCH=guybrush
TEST=Build and boot to OS in Dewatt board version 3.
Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko.
BUG=b:223687184
TEST=emerge-dedede coreboot
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia.
BUG=b:223687184
TEST=emerge-dedede coreboot
Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis.
BUG=b:223687184
TEST=emerge-dedede coreboot
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing
the PSP to hang when resuming from S0ix suspend. The root cause is still
under investigation. Just disabling PSPP fixes the hang but causes poor
PLT performance.
BUG=b:228830362
BRANCH=guybrush
TEST=suspend_stress_test on AC and DC
Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC.
BUG=b:220039297
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: If83031edcd90ea746704590765102b9b0dee03c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.
BUG=b:226684990
TEST=emerge-brya coreboot
Cq-Depend: chrome-internal:4676926, chrome-internal:4686953
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I9852553f5c91494db845d45a94e2566248538bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
MT53E512M32D1NP-046 WT:B (Micron)
MT53E1G32D2NP-046 WT:B (Micron)
H54G46CYRBX267 (Hynix)
H54G56CYRBX247 (Hynix)
K4U6E3S4AB-MGCL (Samsung)
K4UBE3D4AB-MGCL (Samsung)
BUG=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the osiris variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:229352299
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_OSIRIS
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I41e088a3415add86cba87c919af23494f816bb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update SPI setting as below:
Normal speed:33mhz
Fast speed:66mhz
Alt speed:66mz
TPM speed:33mhz
BUG=b:225213679
TEST=boot skyrim and verify spi settings.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Increase RFI Spread Spectrum to 6% for Vell as RF team request. The
default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.
BUG=b:228929196
TEST=emerge-brya coreboot and pass RF test as before
Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function
enable with ALC5682I+MAX98360.
BUG=b:202671753
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Based on the latest schematic, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3
BUG=b:202671753
TEST=emerge-brya coreboot
Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a.
Reason for revert: 100Mhz should only be enabled on DeWatt
on board version >=3. Enabling it on board version 2 will
cause failures.
BUG=b:213403891
BRANCH=guybrush
TEST=Build dewatt
Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This should no longer be needed because the ASL has been fixed.
Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This alias name is required for the mainboard.c code to generate the
appropriate power-off seqeuence for use during orderly S5 shutdown
from the OS. It had been accidentally removed, but is required, so
this patch adds it.
BUG=b:227788351
TEST=compile
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Configure the power saving pin for Smart Card.
BUG=b:229356121
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.
BUG=b:213403891
TEST=Build and boot to OS in Dewatt board version 2.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for felwinter board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379, b:226020977
TEST=Verify the build for felwinter board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add conn1 for pch_espi and add type-c port2 for pmc_mux.
BUG=b:220814038
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence,
the reason is that the rise and fall times of each signal
may differ by board, and so those board-specific delays
must be taken into account when power sequencing.
We checked power on sequence requires enable pin prior to reset pin,
so added delay to meet the sequence.
Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:228907551
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove i2c1 because brask devicetree is already has it.
BUG=b:220814038
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable pen garage. Pen detect is active low.
BUG=b:229168203
TEST:Build and boot to OS in skyrim. Evtest work as expected
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649922170.578779, -------------- SYN_REPORT ------------
Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add Goodix touchscreen according to the Programming Guide Rev.0.7
BUG=b:228907558
TEST=local build and tested with Goodix touch screen
Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is
used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from
PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK.
BUG=b:229345416
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot and verify if the buzzer beeps.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG.
BUG=b:220241277
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icc8fbef1467605505459fce264697f670591c81e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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select DRIVERS_GENESYSLOGIC_GL9750 to disable ASPM L0s.
BUG=b:229213455
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Followed the Brya series to lock the gpio pins in baseboard. Variant
should honor locked gpios from baseboard, but not the last. Variant can
add more gpios to lock if needed.
BUG=b:216671701
TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that
nivviks boots successfully to kernel.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add TPM I2C for crota to avoid TPM I2C fail.
BUG=b:229200525
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add TPM I2C for crota to avoid TPM I2C fail.
BUG=b:226315394
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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update STT setting for dewatt.
BUG=b:228040295
BRANCH=guybrush
TEST=build, verify the parameter has been applied to
the system by checking the AGT tool.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Remove EC_ENABLE_LID_SWITCH since this causes a duplicate SW_LID
entries. The other SW_LID entry is generated by MKBP.
BUG=b:228907256
BRANCH=guybrush
TEST=Lid open close triggers events on Nipperkin
Change-Id: I5c1cf7aeac8405bce7bfc77110eceaf3e5383fe7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:227296841
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
pass PLT criteria: S0 > 600ms, s0i3 > 14 days
Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Set the BT USB device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the BT USB device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.
BRANCH=None
BUG=b:225022810
TEST=Dump SSDT table for guybrush
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Update the build scripts to inject variant specific SPDs into APCB.
BUG=None
TEST=Build and boot to OS in Skyrim boards with all the concerned memory
parts.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63600
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts and generate the associated DRAM part ID.
Also for MT62F2G32D8DR-031 WT:B memory part, add a custom SPD that
configures the DRAM speed at 5500 MHz. Use this custom SPD until that
part can operate at full speed (i.e. 6400 MHz).
BUG=None
TEST=Build Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Setup the following acoustic noise mitigation features:
1) Slew rate for both IA and GT domains to 1/8
2) Disable Fast package C ramp
BUG=b:229046516
TEST=build and verified by power team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ifb5700391e33818878994f205acae7ee3b1b96d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Disable PSPP parameters for WLAN card on Nipperkin. This feature
is causing S0ix resume hangs.
BUG=b:227296841,b:228830362
BRANCH=guybrush
TEST=Suspend stress test passes on Nipperkin
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I38f05b92ace4aba61163194a6a638915882b8871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63593
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some brya variants may need to initialize and finalize some
variant-specific devices during ramstage, therefore add the
commonly-used hooks and callbacks to support this.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:228448327
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
check ACPI device "LCD" in SSDT
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.
BUG=b:223289882
TEST=boot Nipperkin and Dewatt and then verify the devbeep and gpio
values in kernel
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Configure lcnt and hcnt directly to give the required frequency, tHIGH
and tLOW, instead of using rise and fall times. Aim for a frequency of
390 kHz to make sure it doesn't exceed 400 kHz on different boards.
BUG=b:227517802
TEST=Probe the clock line and check that it meets the requirements for
frequency, tHIGH and tLOW.
Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Create the craask variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CRAASK
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Fixes the following build error:
src/mainboard/google/brya/mainboard.c: In function 'variant_generate_s0ix_hook':
src/mainboard/google/brya/mainboard.c:157:40: error: parameter name omitted
void __weak variant_generate_s0ix_hook(enum s0ix_entry)
^~~~~~~~~~~~~~~
BUG=None
TEST=`abuild -a -x -c max -p none -t google/brya` now succeeds
Change-Id: Id578766e2a3b7647e920740dde3e356a7db39d4d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Select the Bayhub LV2 driver, and implement power sequencing as per the
datasheet.
BUG=b:223304542
TEST=Check that connecting an SD card works as expected in the OS. Probe
the EN and RST signals and check the timing requirements are met.
Change-Id: Id1cca2024e06e5b2c7cefd22aa0b735bc542dc3b
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Based on the latest schematic, change MAX98360 AMP interface from I2S2
to I2S1 due to Intel BT offload concern.
BUG=b:202671753
BRANCH=firmware-brya-14505.B
TEST=dmidecode -t 11
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add WWAN power sequence setting to meet spec
BUG=b:220084872
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The workaround causes the eMMC controller to not enter its L1
during the boot process
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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