summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google
Commit message (Collapse)AuthorAgeFilesLines
* qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner2021-08-204-78/+58
| | | | | | | | | | | | | | | | | | | | | | This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Add ALC1019_NAU88L25B supportEric Lai2021-08-203-3/+45
| | | | | | | | | | | | | Add ALC1019_NAU88L25B DB support. BUG=b:195891240 TEST=audio is functional when playing youtube. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/zork: only enable RTD2141 when presentPeter Marheine2021-08-205-1/+55
| | | | | | | | | | | | | | | | | | | An MST hub is only present on some devices that are configured with a particular daughterboard indicated by EC fw_config, so add a fw_config probe that matches the USB daughterboard ID from CBI to only enable it on devices where present, using variant-specific daughterboard IDs. BUG=b:185862297 TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is not present on the same system if probe is changed to enable it for picasso DB. BRANCH=zork Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik2021-08-191-0/+1
| | | | | | | | | | | | | | | This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/driblee: Generate RAM ID and SPD fileFrank Wu2021-08-193-13/+10
| | | | | | | | | | | | | | | | | | | Add the support RAM parts for Driblee. Here is the ram part number list: 1. Hynix H9HCNNNBKMMLXR-NEE 2. Micron MT53E512M32D2NP-046 WT:F 3. Samsung K4U6E3S4AA-MGCR 4. Micron MT53E512M32D1NP-046 WT:B BUG=b:195619346 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: set tcc_offset value to 10Sumeet Pawnikar2021-08-191-0/+2
| | | | | | | | | | | | | | | | | Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUGb=b:195706434 BRANCH=None TEST=Built for brya platform and verified the MSR value Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/primus: Fix GL9755S power sequenceMalik_Hsu2021-08-191-1/+5
| | | | | | | | | | | | | | - Enable EN_PP3300_SD - Configure SD_PE_RST_L correctly BUG=b:195625340 TEST=Able to boot with SD card Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I33c17e88cabdc9b13634fc8f341aa6a09b7bfde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Enable ADL_ENABLE_USB4_PCIE_RESOURCES for primusMalik_Hsu2021-08-191-0/+1
| | | | | | | | | | | | | | | primus supports USB4 and so needs to reserve bus numbers and prefmem and mem resources for potential hotplugs of devices. BUG=b:193377625 BRANCH=None TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I1d1f8cc3460c1b89dade4f01690c77efcd799098 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* google/trogdor: Read SKU ID as binary-first base3 strappingJulius Werner2021-08-191-2/+2
| | | | | | | | | | | We're running out of SKU IDs in the base2 system, so convert it to binary-first base3. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia7f749fa042d3eac76bfe1e74531905c6e279ad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57004 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/sasukette: Add fw_config probe for ALC5682I-VD & VSZhi Li2021-08-183-1/+46
| | | | | | | | | | | | | | | | | | | | Update the `_HID` value of device in SSDT depending on the fw_config. According to value of AUDIO_CODEC_SOURCE field in fw_config(SSFC) which stored in CBI: AUDIO_CODEC_ALC5682: _HID = "10EC5682" /* ALC5682I-VD */ AUDIO_CODEC_ALC5682I_VS: _HID = "RTL5682" /* ALC5682I-VS */ BUG=b:193623380 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
* mb/google/guybrush: Enable STT in device treeJason Glenesk2021-08-181-0/+22
| | | | | | | | | | | | | | | Enable Skin Temperature Tracking with initial configuration settings. BUG=b:190732595 TEST=Confirm that AGT tool can successfully complete data collection Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner2021-08-1816-2277/+15
| | | | | | | | | | | | | | | | | | | | | | All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/octopus/var/phaser: Change IRQ trigger method to levelJoey Peng2021-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | The change from Synaptics S7817 to Elan 3915N and pin distribution of touch IC is the same. The original Elan section was copied from reference design and was never used before. According to vendor spec definition IRQ trigger method needs to change to level. BUG=b:190574692 TEST=Build coreboot and check that device works Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56380 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen2021-08-173-12/+3
| | | | | | | | | | | | | | Add SPD support to lantis for MT53E512M32D1NP-046 WT:B BUG=None BRANCH=firmware-dedede-13606.B TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT failSunwei Li2021-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | irq(ACPI_IRQ_LEVEL_LOW) -> ACPI_DESCRIPTOR_INTERRUPT -> IO-APIC, will assert interrupt frequently; irq_gpio(ACPI_GPIO_IRQ_EDGE_BOTH) -> ACPI_DESCRIPTOR_GPIO -> INT34C8; will not assert interrupt frequently; Because IRQ configuration can't be setted to both EDGE trigger. BUG=b:195635555 BRANCH=dedede TEST=Cirrus audio codec PLT pass Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I65bca519f75af84848284f039b6ad67cb1887823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56973 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* trogdor: Fix "TPM interrupt" lb_gpio to be ACTIVE_HIGHJulius Werner2021-08-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | "Latched" GPIOs like this one are a virtual representation of the pending interrupt flag for the edge-triggered pin and not a direct representation of line state, so they should always be marked ACTIVE_HIGH or depthcharge will incorrectly negate them. This has always been wrong and meant that depthcharge doesn't correctly wait for Cr50 flow control responses on these platforms. Thankfully it doesn't seem like we've seen any practical issues from this, but it's still very wrong. BRANCH=trogdor BUG=none TEST=Booted CoachZ (no visible difference) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie1586b0e10b64df0712e28552411c4d540a7e457 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD devicePatrick Huang2021-08-161-0/+9
| | | | | | | | | | | | | | | | Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device. BUG=b:186384256 BRANCH=none TEST=Verify the config setting can update to the GPPCLKCONTROL registers. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA2021-08-162-4/+0
| | | | | | | | | | | | | | | | | For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA2021-08-162-6/+2
| | | | | | | | | | | | | | | | | | | | coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Create driblee variantFrank Wu2021-08-168-0/+83
| | | | | | | | | | | | | | | | | | Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede: Create corori variantIan Feng2021-08-168-0/+83
| | | | | | | | | | | | | | | | | | Create the corori variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:194356176 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy/variants/atlas: stop setting touchscreen probed=1Matthew Blecker2021-08-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All Atlas devices have the touchscreen controller, so probing for its presence is unnecessary. Removing the probe requirement allows the touchscreen ACPI device in Linux to re-enumerate when rebinding its I2C adapter device. Without this change, after rebinding the touchscreen's I2C adapter device using sysfs the touchscreen ACPI and HID devices are absent, and the touchscreen is unresponsive. With this change, the touchscreen ACPI and HID devices are re-created after rebinding its I2C adapter device, and the touchscreen becomes responsive again. BUG=b:177350937 TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds with Linux 4.4 and 5.4. Built new AP FW from Atlas Chrome OS firmware branch with this change applied. Tested shipping RO + new RW, and new RO + new RW. Test sequence: 1) Boot DUT, verify basic touchscreen functionality. 2) $ cd /sys/bus/platform/drivers/i2c_designware 3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002 drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1 4) $ echo i2c_designware.0 > unbind 5) Verify touchscreen is unresponsive (as expected after unbind). 6) $ ls -ld i2c_designware.0 ls: cannot access 'i2c_designware.0': No such file or directory 7) $ echo i2c_designware.0 > bind *** Without this change: *** 8) Touchscreen remains unresponsive. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}} ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6 *** With this change: *** 8) Touchscreen is functional again. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003 drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen2021-08-163-2/+6
| | | | | | | | | | | | | | | | | Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Add I2C parameterEric Lai2021-08-161-0/+15
| | | | | | | | | | | | | | Add I2C parameters to make sure each bus speed is around 390kHz. BUG=b:188793264 TEST=Measure by scope. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants/kano: Configure GPIOs according to schematicsDavid Wu2021-08-162-0/+135
| | | | | | | | | | | | | Update initial gpio configuration for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Configure EN_FCAM_PWR to highVarshit B Pandya2021-08-161-1/+1
| | | | | | | | | | | | | | | | | Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17 as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and OFF by IPU driver while MIPI UFC probing. However USB UFC also requires 3.3V which is enabled by A17. This caused USB UFC enumeration to fail BUG=b:196014678 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarityCasper Chang2021-08-161-1/+1
| | | | | | | | | | | | | | modify reset_gpio as active low to meet touchscreen spec BUG=b:195490284 BRANCH=none TEST=build coreboot and touchscreen works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: allow MKBP devices and disable TBMC deviceBoris Mittelberg2021-08-161-2/+2
| | | | | | | | | | | | | | | Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Brya P1: Volume Up/Down buttons Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/guybrush: Update GPIOs for fingerprint MCUMartin Roth2021-08-163-10/+46
| | | | | | | | | | | | | | | | | | | | | | Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/brya: set PL4 value dynamically for thermalSumeet Pawnikar2021-08-152-2/+8
| | | | | | | | | | | | | | | | | | | Set PL4 value dynamically for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/{redrix,taeko}: Deduplicate lockdown configFelix Singer2021-08-152-4/+0
| | | | | | | | | | | | Lockdown configuration is done in their baseboards. Thus, remove the setting from the variants overridetree. Change-Id: Iadb1201718466503987e4f6bd72bf711a2d3128e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/google/guybrush: Create nipperkin variantKarthikeyan Ramasubramanian2021-08-139-0/+39
| | | | | | | | | | | | | | | | | | | Create the nipperkin variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_NIPPERKIN Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie525ea501e6c3d5d94e67c1db1d4e307fb7ccba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56921 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/brya0: add PL4 values for different SKUsSumeet Pawnikar2021-08-131-5/+5
| | | | | | | | | | | | | | | | | | Add PL4 values for brya0 board for different CPU SKUs. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5Ivy Jian2021-08-131-2/+2
| | | | | | | | | | | | | | Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to higher value for USB port 5 (Type-A). BUG=b:194053549 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: allow MKBP devices and disable TBMC deviceBoris Mittelberg2021-08-131-3/+3
| | | | | | | | | | | | | | | | | Enable MKBP (Matrix Keyboard Protocol) interface for all dedede family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Madoo: Volume Up/Down and Power buttons, Tablet Mode switch Cq-Depend: chromium:3069163 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I9d1f43e4dd56318af4c1d5f5c1c3a2c237a05c5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56840 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/galtic: Add charger throttling functionFrankChu2021-08-121-1/+9
| | | | | | | | | | | | | | | | | | | | Add charger current throttling support for galtic control charger index * 64 = Value mA 32*64=2048 28*64=1792 24*64=1536 20*64=1280 BUG=b:187231627 TEST=Built and tested on boten system Cq-Depend: chrome-internal:3846209 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/dedede/variants/haboki: add discrete TPM in overridetreeWisley Chen2021-08-121-4/+9
| | | | | | | | | | | | | | | Haboki is project which use discrete TPM, so add discrete TPM and disable cr50 in overrideree. BUG=b:187094464 TEST=FW_NAME=haboki emerge-keeby coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I08f2a562c3f62c60402350151ea260b70890a744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/variants/redrix: enable LTE PCIe portWisley Chen2021-08-121-0/+3
| | | | | | | | | | | | | | | Enable LTE PCIe port according to fw config. BUG=b:192052098 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ic9472d2249c622858a75c63bc82e8e4e8166a3d7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/redrix: add mipi camera supportWisley Chen2021-08-122-0/+73
| | | | | | | | | | | | | | | Add mipi camera support by selecting the Kconfig symbols and adding it to the devicetree with ACPI UID 0x50000 and name IPU0. BUG=b:192052098 TEST=checked mipi camera works Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I69281f36ddbc1abf9905c8db9287500f9aa995c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56893 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enableMark Hsieh2021-08-121-0/+2
| | | | | | | | | | | | | | add GPP_D16 in gimle gpio.c and set value to 1 for PP1800 DMIC init sequence BUG=b:195968649 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia0639162e2c3f02f622470fa16c21fe8a067cf7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56889 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/trogdor: Add new variant WormdinglerZanxi Chen2021-08-122-0/+5
| | | | | | | | | | | | | | New board introduced to trogdor family. BUG=b:193870279 BRANCH=none TEST=make Change-Id: If3d9662e8725e30e1308d77b05545efbee29f846 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/variant/taeko: Update devicetree settingsJoey Peng2021-08-111-2/+277
| | | | | | | | | | | | | | Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/cret: Fix DPTF passive and critical policiesDtrain Hsu2021-08-101-0/+36
| | | | | | | | | | | | | | | | | | TSR2 thermal sensor doesn't define in cret. Fix DPTF passive and critical policies for getting negative temperatures in OS. BUG=b:195868075 BRANCH=dedede TEST=Build and boot to OS in cret. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I849662cbb3adc8e528d65af2c90e7c8e4880d607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/brya/variants/primus: Remove DPTF fan controlScott Chao2021-08-101-32/+0
| | | | | | | | | | | | | BUG=b:195901486, b:195387997 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If758d75ff24c88c9eaf0de90ac0ef08d172a2edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56879 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA2021-08-102-4/+0
| | | | | | | | | | | | | | | | | | For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/brya/adlrvp: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA2021-08-102-6/+4
| | | | | | | | | | | | | | | | | | | | | coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/hatch/scout: Update DPTF parametersKenneth Chan2021-08-101-8/+10
| | | | | | | | | | | | | | | update the DPTF parameters received from the thermal team. BUG=b:195602767 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I5dc89d1d4c2b64c9aac780a7db743a91fd0ebc9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeff Chase <jnchase@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codecSunwei Li2021-08-103-2/+63
| | | | | | | | | | | | | | | | | Compatible headphone codec "Realtek ALC5682I-VD" and "cirrus CS42L42" Compatible AMP codec "ALC1015Q-VB" and "MAX98360" BUG=b:193373320 BRANCH=dedede TEST=Both realtek and cirrus audio codec can work normally Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I9121e75eaf46b43e6dc5ef2e31029a153c7a807d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* mb/google/brya/variant/taeko: Update memory settingsJoey Peng2021-08-105-13/+113
| | | | | | | | | | | | | Based on the Taeko's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/storo: Fixed iasl can not run on DutTao Xia2021-08-091-1/+1
| | | | | | | | | | | | | | | | | | The TSR1._PSV has been redefined. It will report errors when disassembling the ACPI tables with the iasl. It is OK when Removing the TSR1._PSV and adding the TSR0._PSV BUG=b:194509417 BRANCH=dedede TEST=The iasl can run on Dut successfully Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I524255c79d3c71573d122944da5058389f79d95d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Evan Green <evgreen@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-27 17:51:27 +0000