| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/alderlake: Factor out A0 stepping workaround | Angel Pons | 2022-01-11 | 1 | -86/+0 |
| * | mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h' | Subrata Banik | 2021-07-19 | 1 | -1/+1 |
| * | mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon | Sridhar Siricilla | 2021-07-17 | 1 | -0/+86 |
| * | mb/intel/adlrvp: do UART pad config at board-level | Michael Niewöhner | 2021-03-12 | 1 | -1/+1 |
| * | mb/intel/adlrvp/bootblock.c: Remove unused includes | Elyes HAOUAS | 2021-02-10 | 1 | -1/+0 |
| * | mb/intel/adlrvp: Add initial ADL-P mainboard code | Subrata Banik | 2020-10-08 | 1 | -0/+10 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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