| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ChromeOS: Refactor ACPI CNVS generation | Kyösti Mälkki | 2021-12-23 | 1 | -3/+0 |
| * | mb/intel/adlrvp: Use dedicated VBT files for ADL-M | Bernardo Perez Priego | 2021-11-22 | 1 | -2/+3 |
| * | mb/intel/adlrvp: create dynamic power limits mechanism for thermal | Sumeet Pawnikar | 2021-08-10 | 1 | -0/+7 |
| * | mb/intel/adlrvp: Support VBT binaries for LP4 and LP5 | Bernardo Perez Priego | 2021-08-09 | 1 | -0/+3 |
| * | mb/intel/adlrvp: Add probed fw_configs to SMBIOS OEM strings | Anil Kumar | 2021-08-05 | 1 | -1/+23 |
| * | mb/intel/adlrvp: Add board id for MR DDR5 SKU | Deepti Deshatty | 2021-06-14 | 1 | -1/+2 |
| * | mb/intel/adlrvp: Update VBT filenames | Tim Wawrzynczak | 2021-04-02 | 1 | -2/+2 |
| * | mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs | Meera Ravindranath | 2021-03-15 | 1 | -0/+15 |
| * | mb/intel/adlrvp: Add ADL-P ramstage mainboard code | Subrata Banik | 2020-10-14 | 1 | -0/+40 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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