coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`4.10	Nico Huber	2019-07-20	1	-1/+0
*	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans	2019-06-06	1	-1/+0
*	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans	2019-06-05	1	-2/+0
*	mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetree	Arthur Heymans	2019-01-08	1	-1/+1
*	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans	2018-11-12	1	-10/+9
*	mb/intel: Get rid of whitespace before tab	Elyes HAOUAS	2018-06-04	1	-10/+10
*	nb/intel/i945: Make pci_mmio_size a devicetree parameter	Arthur Heymans	2016-12-11	1	-0/+2
*	mb/intel/d945gclf: Disable combined mode to fix SATA	Arthur Heymans	2016-09-07	1	-1/+1
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	1	-4/+0
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	1	-1/+1
*	i82801gx: Handle whole FADT in southbridge.	Vladimir Serbinenko	2014-11-04	1	-0/+2
*	sconfig: rename lapic_cluster -> cpu_cluster	Stefan Reinauer	2013-02-14	1	-1/+1
*	sconfig: rename pci_domain -> domain	Stefan Reinauer	2013-02-14	1	-1/+1
*	Use subsystem id from devicetree.cb instead of Kconfig and move	Sven Schnelle	2011-03-01	1	-0/+1
*	Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"	Patrick Georgi	2010-05-05	1	-2/+2
*	Since some people disapprove of white space cleanups mixed in regular commits	Stefan Reinauer	2010-04-27	1	-3/+3
*	Remove drivers/pci/onboard. The only purpose was for option ROMs, which are	Myles Watson	2009-11-06	1	-3/+1
*	Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.	Uwe Hermann	2009-11-06	1	-3/+0
*	Add some missing license headers, consistency fixes for others (trivial).	Uwe Hermann	2009-10-28	1	-4/+2
*	preliminary Intel D945GCLF Atom+i945 support.	Stefan Reinauer	2009-10-28	1	-0/+115