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* mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1112-12/+0
* src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS2020-05-101-13/+1
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-092-18/+2
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-062-24/+2
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-062-4/+2
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-022-2/+2
* mainboard/intel: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-066-77/+12
* mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons2020-03-201-12/+1
* mainboard/[g-p]*: Remove copyright noticesPatrick Georgi2020-03-1810-15/+0
* mb/intel/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS2020-01-131-1/+0
* mb/*/*/acpi_tables: Remove unused includesElyes HAOUAS2020-01-021-1/+0
* mb/*/*/acpi_tables: Don't zero out gnvs againPeter Lemenkov2019-12-311-2/+0
* mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons2019-12-311-1/+0
* arch/x86: Make X86 stages select ARCH_X86Arthur Heymans2019-12-161-1/+0
* nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-152-1/+5
* nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans2019-11-151-36/+6
* mb/*/*(ich7/x4x): Use common early southbridge initArthur Heymans2019-11-141-13/+1
* sb/intel/i82801gx: Add common LPC decode codeArthur Heymans2019-11-122-14/+3
* mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'Elyes HAOUAS2019-11-111-1/+0
* mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.aslArthur Heymans2019-11-042-29/+1
* mb/intel/{i82801gx,x4x}: Don't select ASPM optionsArthur Heymans2019-11-031-3/+0
* soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik2019-11-011-1/+1
* sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans2019-10-111-5/+1
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-1/+1
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-3/+1
* sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans2019-06-061-1/+0
* mb/*/devicetree.cb: Remove unavailable PCIe portsArthur Heymans2019-06-051-2/+0
* sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph2019-04-131-0/+1
* {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS2019-03-131-2/+0
* device/pnp: Add header files for PNP opsKyösti Mälkki2019-03-041-1/+1
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* mb/{asrock,intel,kontron}: Include missing <arch/io.h>Elyes HAOUAS2019-02-081-6/+7
* src: Remove unused include device/pnp_def.hElyes HAOUAS2019-02-071-1/+0
* mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS2019-01-101-7/+0
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-091-3/+0
* sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans2019-01-081-2/+0
* arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki2018-12-281-1/+0
* mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS2018-11-231-2/+3
* ACPI: Fix DSDT's revision fieldElyes HAOUAS2018-11-211-1/+1
* mb/*/*/cmos.default: Decrease debug_level to 'Debug'Elyes HAOUAS2018-08-151-1/+1
* mb: Get rid of unneeded include <cbmem.h>Elyes HAOUAS2018-08-131-1/+0
* mb/intel/dg41wv: Expose some SIO devices via ACPIArthur Heymans2018-07-031-1/+28
* src/mb: Fix non-local header treated as localElyes HAOUAS2018-07-021-2/+1
* sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans2018-06-291-66/+0
* nb/intel/x4x: Deprecate native graphic initArthur Heymans2018-06-141-2/+0
* mb/*/*: Enable libgfxinit on x4x boardsArthur Heymans2018-06-143-0/+30
* drivers/intel/gma: Unify VBT related Kconfig namesNico Huber2018-06-121-1/+1
* mb/*/*: Add a few VBT filesArthur Heymans2018-06-062-0/+1
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